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1 #-----------------------------------------------------------------------------
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2 # MS Visual C makefile for compiling and testing the G.726
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3 # implementation.
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4 # The executable must be defined by variable G726 below.
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5 # History:
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6 # 31.Jan.2000 - Implemented by <simao.campos@labs.comsat.com>
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7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
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8 # order to perform the (optional) compliance test.
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9 #-----------------------------------------------------------------------------
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10
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11 # ------------------------------------------------
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12 # Choose compiler.
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13 # ------------------------------------------------
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14 CC=cl
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15 CC_OPT = -I../utl /Yd /DEBUG
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16
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17 # ------------------------------------------------
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18 # General purpose symbols
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19 # ------------------------------------------------
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20 G726 = g726demo
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21 VBR = vbr-g726 -q
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22 DIFF = cf -q
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23 RM=rm -f
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24
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25 # ------------------------------------------------
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26 # Choose an archiving utility:
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27 # - public domain unzip, or [PC/Unix/VMS]
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28 # - shareware pkunzip [PC only]
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29 # ------------------------------------------------
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30 #UNZIP = pkunzip
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31 UNZIP = unzip -o
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32
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33 # ------------------------------------------------
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34 # File lists
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35 # ------------------------------------------------
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36 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
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37
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38 DEMO_OBJ = g726demo.obj g726.obj
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39 VBR_OBJ = vbr-g726.obj g726.obj g711.obj
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40
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41 # ------------------------------------------------
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42 # Targets
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43 # ------------------------------------------------
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44 all:: g726demo vbr-g726
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45
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46 anyway: clean all
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47
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48 clean:
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49 $(RM) *.obj
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50
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51 cleantest:
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52 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
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53 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
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54
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55 veryclean: clean cleantest
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56 $(RM) g726demo.exe vbr-g726.exe
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57
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58 # -----------------------------------------------------------------------------
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59 # Generic rules
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60 # -----------------------------------------------------------------------------
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61 .c.obj:
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62 $(CC) $(CC_OPT) -c $<
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63
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64 # -----------------------------------------------------------------------------
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65 # Specific rules
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66 # -----------------------------------------------------------------------------
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67 vbr-g726: vbr-g726.exe
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68 g726demo: g726demo.exe
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69 vbr-g726.exe: $(VBR_OBJ)
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70 $(CC) -o vbr-g726 $(CC_OPT) $(VBR_OBJ)
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71
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72 g726demo.exe: $(DEMO_OBJ)
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73 $(CC) -o g726demo $(CC_OPT) $(DEMO_OBJ)
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74
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75 g726demo.obj: g726demo.c
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76 $(CC) -c $(CC_OPT) -I../g711 g726demo.c
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77
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78 g726.obj: g726.c
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79 $(CC) -c $(CC_OPT) g726.c
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80
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81 g711.obj: ../g711/g711.c
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82 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
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83
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84 vbr-g726.obj: vbr-g726.c
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85 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
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86
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87 # ----------------------------------------
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88 # Very simple portability test
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89 # ----------------------------------------
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90 test: test-vbr-quick
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91 proc: proc-vbr-quick
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92 comp: comp-vbr-quick
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93
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94 test-vbr-quick: proc-vbr-quick comp-vbr-quick
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95 proc-vbr-quick: voice.src
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96 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
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97 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
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98 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
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99 comp-vbr-quick: voicevbr.arf
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100 $(DIFF) voicvbra.tst voicevbr.arf
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101 $(DIFF) voicvbrl.tst voicevbr.lrf
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102 $(DIFF) voicvbru.tst voicevbr.urf
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103
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104 voice.src: tst-g726.zip
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105 $(UNZIP) tst-g726.zip voice.src
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106 sb -over voice.src
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107
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108 voicevbr.arf: tst-g726.zip
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109 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
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110 swapover voicevbr.arf voicevbr.lrf voicevbr.urf
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111
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112 # -----------------------------------------------------------------------------
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113 # Test the implementation for g726demo (compliance)
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114 # In the automatic compliance testing, g726demo.c is verified by test-tv
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115 # For vbr-g726.c, no differences should be observed, since both use g726.c,
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116 # and differ only on the demo logic. For full compliance testing of the
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117 # vbr-g726.c program, use test-tv-vbr
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118 # -----------------------------------------------------------------------------
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119 test-tv: proc-tv-fix comp-tv
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120 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
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121 comp-tv-fix: comp-tv
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122 comp-tv: comp16 comp24 comp32 comp40
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123
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124 proc16-fix:
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125 #
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126 # Process ADPCM/ Coder for normal and overload sequences, A law
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127 #
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128 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
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129 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
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130 #
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131 # Process ADPCM/ Decoder for normal and overload sequences, A law
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132 #
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133 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
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134 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
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135 #
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136 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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137 # A law input -> ADPCM 16kbit/s -> mu law output
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138 #
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139 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
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140 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
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141 #
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142 #
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143 # Process ADPCM/ Coder for normal and overload sequences, mu law
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144 #
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145 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
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146 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
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147 #
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148 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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149 #
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150 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
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151 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
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152 #
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153 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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154 # mu law input -> ADPCM 16kbit/s -> A law output
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155 #
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156 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
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157 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
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158 #
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159 #
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160 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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161 #
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162 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
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163 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
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164
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165 comp16:
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166 #
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167 # =================================================================
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168 # COMPARISON OF FILES !
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169 # =================================================================
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170 #
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171 # Compare ADPCM/ Coder for normal and overload sequences, A law
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172 #
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173 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
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174 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
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175 #
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176 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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177 #
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178 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
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179 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
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180 #
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181 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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182 # A law input -> ADPCM x kbit/s -> mu law output
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183 #
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184 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
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185 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
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186 #
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187 #
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188 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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189 #
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190 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
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191 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
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192 #
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193 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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194 #
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195 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
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196 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
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197 #
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198 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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199 # mu law input -> ADPCM x kbit/s -> A law output
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200 #
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201 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
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202 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
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203 #
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204 #
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205 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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206 #
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207 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
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208 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
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209
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210 proc24-fix:
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211 #
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212 #
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213 # Process ADPCM/ Coder for normal and overload sequences, A law
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214 #
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215 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
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216 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
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217 #
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218 # Process ADPCM/ Decoder for normal and overload sequences, A law
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219 #
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220 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
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221 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
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222 #
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223 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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224 # A law input -> ADPCM 24kbit/s -> mu law output
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225 #
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226 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
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227 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
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228 #
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229 #
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230 # Process ADPCM/ Coder for normal and overload sequences, mu law
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231 #
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232 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
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233 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
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234 #
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235 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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236 #
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237 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
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238 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
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239 #
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240 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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241 # mu law input -> ADPCM 24kbit/s -> A law output
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242 #
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243 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
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244 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
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245 #
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246 #
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247 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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248 #
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249 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
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250 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
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251
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252 comp24:
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253 #
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254 # =================================================================
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255 # COMPARISON OF FILES !
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256 # =================================================================
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257 #
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258 # Compare ADPCM/ Coder for normal and overload sequences, A law
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259 #
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260 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
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261 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
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262 #
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263 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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264 #
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265 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
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266 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
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267 #
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268 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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269 # A law input -> ADPCM x kbit/s -> mu law output
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270 #
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271 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
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272 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
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273 #
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274 #
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275 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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276 #
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277 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
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278 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
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279 #
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280 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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281 #
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282 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
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283 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
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284 #
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285 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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286 # mu law input -> ADPCM x kbit/s -> A law output
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287 #
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288 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
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289 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
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290 #
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291 #
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292 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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293 #
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294 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
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295 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
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296
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297 proc32-fix:
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298 #
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299 # Process ADPCM/ Coder for normal and overload sequences, A law
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300 #
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301 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
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302 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
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303 #
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304 # Process ADPCM/ Decoder for normal and overload sequences, A law
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305 #
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306 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
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307 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
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308 #
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309 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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310 # A law input -> ADPCM 32kbit/s -> mu law output
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311 #
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312 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
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313 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
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314 #
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315 #
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316 # Process ADPCM/ Coder for normal and overload sequences, mu law
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317 #
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318 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
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319 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
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320 #
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321 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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322 #
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323 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
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324 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
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325 #
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326 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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327 # mu law input -> ADPCM 32kbit/s -> A law output
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328 #
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329 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
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330 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
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331 #
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332 #
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333 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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334 #
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335 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
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336 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
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337
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338 comp32:
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339 #
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340 # =================================================================
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341 # COMPARISON OF FILES !
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342 # =================================================================
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343 #
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344 # Compare ADPCM/ Coder for normal and overload sequences, A law
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345 #
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346 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
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347 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
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348 #
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349 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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350 #
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351 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
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352 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
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353 #
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354 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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355 # A law input -> ADPCM x kbit/s -> mu law output
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356 #
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357 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
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358 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
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359 #
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360 #
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361 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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362 #
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363 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
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364 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
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365 #
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366 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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367 #
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368 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
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369 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
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370 #
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371 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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372 # mu law input -> ADPCM x kbit/s -> A law output
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373 #
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374 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
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375 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
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376 #
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377 #
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378 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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379 #
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380 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
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381 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
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382
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383 proc40-fix:
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384 #
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385 #
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386 # Process ADPCM/ Coder for normal and overload sequences, A law
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387 #
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388 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
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389 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
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390 #
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391 # Process ADPCM/ Decoder for normal and overload sequences, A law
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392 #
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393 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
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394 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
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395 #
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396 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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397 # A law input -> ADPCM 40kbit/s -> mu law output
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398 #
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399 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
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400 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
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401 #
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402 #
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403 # Process ADPCM/ Coder for normal and overload sequences, mu law
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404 #
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405 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
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406 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
|
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|
407 #
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408 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
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409 #
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410 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
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411 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
|
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412 #
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413 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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414 # mu law input -> ADPCM 40kbit/s -> A law output
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415 #
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416 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
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417 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
|
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418 #
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|
419 #
|
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420 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
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421 #
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422 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
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|
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423 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
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424
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425 comp40:
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426 #
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|
427 # =================================================================
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428 # COMPARISON OF FILES !
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|
429 # =================================================================
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|
430 #
|
|
|
431 # Compare ADPCM/ Coder for normal and overload sequences, A law
|
|
|
432 #
|
|
|
433 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
|
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434 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
|
|
|
435 #
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|
|
436 # Compare ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
437 #
|
|
|
438 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
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439 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
|
|
|
440 #
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|
|
441 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
442 # A law input -> ADPCM x kbit/s -> mu law output
|
|
|
443 #
|
|
|
444 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
|
|
|
445 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
|
|
|
446 #
|
|
|
447 #
|
|
|
448 # Compare ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
449 #
|
|
|
450 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
|
|
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451 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
|
|
|
452 #
|
|
|
453 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
454 #
|
|
|
455 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
|
|
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456 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
|
|
|
457 #
|
|
|
458 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
459 # mu law input -> ADPCM x kbit/s -> A law output
|
|
|
460 #
|
|
|
461 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
|
|
|
462 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
|
|
|
463 #
|
|
|
464 #
|
|
|
465 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
466 #
|
|
|
467 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
|
|
|
468 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
|
|
|
469
|
|
|
470 #
|
|
|
471 # ----------------------------------------------------------------------------
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|
|
472 # Test the implementation for vbr-g726 (compliance)
|
|
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473 # ----------------------------------------------------------------------------
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474 test-tv-vbr: proc-tv-vbr comp-tv
|
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475 proc-tv-vbr: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
|
|
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476 comp-vbr-tv: comp-tv
|
|
|
477
|
|
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478 proc16-vbr:
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|
|
479 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
480 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
|
|
|
481 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
|
|
|
482 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
483 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
|
|
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484 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
|
|
|
485 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
486 # A law input -> ADPCM 16kbit/s -> mu law output
|
|
|
487 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
|
|
|
488 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
|
|
|
489 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
490 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
|
|
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491 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
|
|
|
492 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
493 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
|
|
|
494 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
|
|
|
495 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
496 # mu law input -> ADPCM 16kbit/s ->A law output
|
|
|
497 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
|
|
|
498 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
|
|
|
499 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
500 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
|
|
|
501 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
|
|
|
502
|
|
|
503 proc24-vbr:
|
|
|
504 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
505 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
|
|
|
506 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
|
|
|
507 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
508 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
|
|
|
509 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
|
|
|
510 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
511 # A law input -> ADPCM 24kbit/s -> mu law output
|
|
|
512 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
|
|
|
513 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
|
|
|
514 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
515 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
|
|
|
516 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
|
|
|
517 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
518 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
|
|
|
519 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
|
|
|
520 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
521 # mu law input -> ADPCM 24kbit/s ->A law output
|
|
|
522 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
|
|
|
523 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
|
|
|
524 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
525 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
|
|
|
526 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
|
|
|
527
|
|
|
528 proc32-vbr:
|
|
|
529 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
530 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
|
|
|
531 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
|
|
|
532 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
533 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
|
|
|
534 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
|
|
|
535 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
536 # A law input -> ADPCM 32kbit/s -> mu law output
|
|
|
537 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
|
|
|
538 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
|
|
|
539 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
540 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
|
|
|
541 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
|
|
|
542 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
543 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
|
|
|
544 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
|
|
|
545 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
546 # mu law input -> ADPCM 32kbit/s ->A law output
|
|
|
547 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
|
|
|
548 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
|
|
|
549 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
550 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
|
|
|
551 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
|
|
|
552
|
|
|
553 proc40-vbr:
|
|
|
554 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
555 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
|
|
|
556 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
|
|
|
557 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
558 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
|
|
|
559 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
|
|
|
560 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
561 # A law input -> ADPCM 40kbit/s -> mu law output
|
|
|
562 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
|
|
|
563 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
|
|
|
564 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
565 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
|
|
|
566 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
|
|
|
567 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
568 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
|
|
|
569 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
|
|
|
570 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
571 # mu law input -> ADPCM 40kbit/s ->A law output
|
|
|
572 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
|
|
|
573 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
|
|
|
574 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
575 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
|
|
|
576 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
|
|
|
577
|
|
|
578 # =========================================
|
|
|
579 # Process by batch
|
|
|
580 # =========================================
|
|
|
581 batchtest:
|
|
|
582 batch test-g726
|
|
|
583
|
|
|
584 batchtest-vbr:
|
|
|
585 echo make -f makefile.unx test-vbr | batch
|
