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1 # -----------------------------------------------------------------------------
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2 # Unix makefile for compiling and testing the G.726 implementation
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3 # The executable must be defined by variable G726 below.
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4 # 01.May.94 - Implemented by <simao@cpqd.ansp.br>
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5 # 10.Mar.95 - Compilation and test sequence processing/comparison for
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6 # vbr-g726.c. <simao@ctd.comsat.com>
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7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
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8 # order to perform the (optional) compliance test.
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9 # -----------------------------------------------------------------------------
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10
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11 # ------------------------------------------------
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12 # Choose compiler. Sun: use cc. HP: gotta use gcc
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13 # ------------------------------------------------
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14 CC=gcc
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15 CC_OPT = -Wall -g -I../utl
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16
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17 # ------------------------------------------------
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18 # General purpose symbols
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19 # ------------------------------------------------
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20 G726 = ./g726demo
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21 VBR = ./vbr-g726 -q
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22 # DIFF = cf -q
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23 DIFF = diff
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24
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25 # ------------------------------------------------
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26 # Choose an archiving utility:
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27 # - public domain unzip, or [PC/Unix/VMS]
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28 # - shareware pkunzip [PC only]
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29 # ------------------------------------------------
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30 #UNZIP = pkunzip
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31 UNZIP = unzip -o
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32
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33 # ------------------------------------------------
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34 # File lists
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35 # ------------------------------------------------
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36 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
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37
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38 DEMO_OBJ = g726demo.o g726.o
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39 VBR_OBJ = vbr-g726.o g726.o g711.o
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40
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41 # ------------------------------------------------
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42 # Targets
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43 # ------------------------------------------------
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44 all:: g726demo vbr-g726
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45
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46 anyway: clean all
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47
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48 clean:
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49 $(RM) *.o
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50
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51 cleantest:
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52 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
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53 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
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54
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55 veryclean: clean cleantest
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56 $(RM) g726demo vbr-g726
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57
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58 # -----------------------------------------------------------------------------
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59 # Generic rules
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60 # -----------------------------------------------------------------------------
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61 .c.o:
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62 $(CC) $(CC_OPT) -c $<
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63
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64 # -----------------------------------------------------------------------------
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65 # Specific rules
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66 # -----------------------------------------------------------------------------
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67 vbr-g726: $(VBR_OBJ)
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68 $(CC) -o vbr-g726 $(VBR_OBJ) -lm
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69
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70 g726demo: $(DEMO_OBJ)
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71 $(CC) -o g726demo $(DEMO_OBJ) -lm
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72
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73 g726demo.o: g726demo.c
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74 $(CC) -c $(CC_OPT) -I../g711 g726demo.c
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75
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76 g726.o: g726.c
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77 $(CC) -c $(CC_OPT) g726.c
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78
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79 g711.o: ../g711/g711.c
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80 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
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81
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82 vbr-g726.o: vbr-g726.c
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83 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
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84
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85 # ----------------------------------------
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86 # Very simple portability test
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87 # ----------------------------------------
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88 test: test-vbr-quick
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89 proc: proc-vbr-quick
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90 comp: comp-vbr-quick
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91
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92 test-vbr-quick: proc-vbr-quick comp-vbr-quick
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93 proc-vbr-quick: voice.src
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94 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
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95 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
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96 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
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97 comp-vbr-quick: voicevbr.arf
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98 $(DIFF) voicvbra.tst voicevbr.arf
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99 $(DIFF) voicvbrl.tst voicevbr.lrf
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100 $(DIFF) voicvbru.tst voicevbr.urf
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101
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102 voice.src: tst-g726.zip
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103 $(UNZIP) tst-g726.zip voice.src
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104 sb -over -if little voice.src
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105
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106 voicevbr.arf: tst-g726.zip
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107 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
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108 swapover -if little voicevbr.arf voicevbr.lrf voicevbr.urf
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109
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110 # -----------------------------------------------------------------------------
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111 # Test the implementation for g726demo (compliance)
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112 # In the automatic compliance testing, g726demo.c is verified by test-tv
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113 # For vbr-g726.c, no differences should be observed, since both use g726.c,
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114 # and differ only on the demo logic. For full compliance testing of the
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115 # vbr-g726.c program, use test-tv-vbr
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116 # -----------------------------------------------------------------------------
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117 test-tv: proc-tv-fix comp-tv
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118 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
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119 comp-tv-fix: comp-tv
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120 comp-tv: comp16 comp24 comp32 comp40
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121
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122 proc16-fix:
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123 #
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124 # Process ADPCM/ Coder for normal and overload sequences, A law
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125 #
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126 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
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127 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
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128 #
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129 # Process ADPCM/ Decoder for normal and overload sequences, A law
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130 #
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131 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
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132 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
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133 #
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134 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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135 # A law input -> ADPCM 16kbit/s -> mu law output
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136 #
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137 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
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138 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
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139 #
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140 #
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141 # Process ADPCM/ Coder for normal and overload sequences, mu law
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142 #
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143 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
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144 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
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145 #
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146 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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147 #
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148 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
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149 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
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150 #
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151 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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152 # mu law input -> ADPCM 16kbit/s -> A law output
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153 #
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154 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
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155 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
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156 #
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157 #
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158 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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159 #
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160 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
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161 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
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162
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163 comp16:
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164 #
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165 # =================================================================
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166 # COMPARISON OF FILES !
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167 # =================================================================
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168 #
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169 # Compare ADPCM/ Coder for normal and overload sequences, A law
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170 #
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171 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
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172 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
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173 #
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174 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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175 #
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176 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
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177 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
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178 #
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179 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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180 # A law input -> ADPCM x kbit/s -> mu law output
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181 #
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182 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
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183 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
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184 #
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185 #
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186 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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187 #
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188 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
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189 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
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190 #
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191 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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192 #
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193 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
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194 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
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195 #
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196 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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197 # mu law input -> ADPCM x kbit/s -> A law output
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198 #
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199 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
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200 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
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201 #
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202 #
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203 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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204 #
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205 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
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206 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
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207
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208 proc24-fix:
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209 #
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210 #
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211 # Process ADPCM/ Coder for normal and overload sequences, A law
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212 #
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213 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
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214 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
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215 #
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216 # Process ADPCM/ Decoder for normal and overload sequences, A law
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217 #
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218 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
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219 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
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220 #
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221 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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222 # A law input -> ADPCM 24kbit/s -> mu law output
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223 #
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224 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
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225 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
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226 #
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227 #
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228 # Process ADPCM/ Coder for normal and overload sequences, mu law
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229 #
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230 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
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231 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
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232 #
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233 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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234 #
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235 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
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236 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
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237 #
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238 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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239 # mu law input -> ADPCM 24kbit/s -> A law output
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240 #
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241 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
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242 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
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243 #
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244 #
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245 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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246 #
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247 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
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248 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
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249
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250 comp24:
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251 #
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252 # =================================================================
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253 # COMPARISON OF FILES !
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254 # =================================================================
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255 #
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256 # Compare ADPCM/ Coder for normal and overload sequences, A law
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257 #
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258 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
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259 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
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260 #
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261 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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262 #
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263 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
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264 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
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265 #
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266 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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267 # A law input -> ADPCM x kbit/s -> mu law output
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268 #
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269 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
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270 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
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271 #
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272 #
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273 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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274 #
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275 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
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276 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
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277 #
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278 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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279 #
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280 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
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281 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
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282 #
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283 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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284 # mu law input -> ADPCM x kbit/s -> A law output
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285 #
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286 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
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287 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
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288 #
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289 #
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290 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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291 #
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292 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
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293 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
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294
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295 proc32-fix:
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296 #
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297 # Process ADPCM/ Coder for normal and overload sequences, A law
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298 #
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299 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
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300 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
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301 #
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302 # Process ADPCM/ Decoder for normal and overload sequences, A law
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303 #
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304 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
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305 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
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306 #
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307 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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308 # A law input -> ADPCM 32kbit/s -> mu law output
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309 #
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310 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
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311 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
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312 #
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313 #
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314 # Process ADPCM/ Coder for normal and overload sequences, mu law
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315 #
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316 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
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317 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
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318 #
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319 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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320 #
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321 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
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322 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
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323 #
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324 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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325 # mu law input -> ADPCM 32kbit/s -> A law output
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326 #
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327 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
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328 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
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329 #
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330 #
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331 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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332 #
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333 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
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334 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
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335
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336 comp32:
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337 #
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338 # =================================================================
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339 # COMPARISON OF FILES !
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340 # =================================================================
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341 #
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342 # Compare ADPCM/ Coder for normal and overload sequences, A law
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343 #
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344 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
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345 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
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346 #
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347 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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348 #
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349 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
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350 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
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351 #
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352 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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353 # A law input -> ADPCM x kbit/s -> mu law output
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354 #
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355 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
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356 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
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357 #
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358 #
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359 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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360 #
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361 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
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362 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
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363 #
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364 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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365 #
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366 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
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367 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
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368 #
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369 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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370 # mu law input -> ADPCM x kbit/s -> A law output
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371 #
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372 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
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373 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
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374 #
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375 #
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376 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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377 #
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378 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
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379 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
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380
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381 proc40-fix:
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382 #
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383 #
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384 # Process ADPCM/ Coder for normal and overload sequences, A law
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385 #
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386 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
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387 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
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388 #
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389 # Process ADPCM/ Decoder for normal and overload sequences, A law
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390 #
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391 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
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392 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
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393 #
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394 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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395 # A law input -> ADPCM 40kbit/s -> mu law output
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396 #
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397 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
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398 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
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399 #
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400 #
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401 # Process ADPCM/ Coder for normal and overload sequences, mu law
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402 #
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403 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
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404 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
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405 #
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406 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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407 #
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408 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
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409 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
|
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410 #
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411 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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412 # mu law input -> ADPCM 40kbit/s -> A law output
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413 #
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414 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
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415 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
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416 #
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417 #
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418 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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419 #
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420 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
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421 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
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422
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423 comp40:
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424 #
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425 # =================================================================
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426 # COMPARISON OF FILES !
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427 # =================================================================
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428 #
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429 # Compare ADPCM/ Coder for normal and overload sequences, A law
|
|
|
430 #
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|
431 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
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432 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
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433 #
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434 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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|
435 #
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|
436 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
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437 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
|
|
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438 #
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439 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
440 # A law input -> ADPCM x kbit/s -> mu law output
|
|
|
441 #
|
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|
442 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
|
|
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443 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
|
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|
444 #
|
|
|
445 #
|
|
|
446 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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|
|
447 #
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|
|
448 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
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449 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
|
|
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450 #
|
|
|
451 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
452 #
|
|
|
453 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
|
|
|
454 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
|
|
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455 #
|
|
|
456 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
457 # mu law input -> ADPCM x kbit/s -> A law output
|
|
|
458 #
|
|
|
459 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
|
|
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460 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
|
|
|
461 #
|
|
|
462 #
|
|
|
463 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
464 #
|
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|
465 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
|
|
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466 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
|
|
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467
|
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468 #
|
|
|
469 # ----------------------------------------------------------------------------
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470 # Test the implementation for vbr-g726 (compliance)
|
|
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471 # ----------------------------------------------------------------------------
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472 test-vbr: proc-vbr comp-tv
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473 proc-vbr: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
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474 comp-vbr-tv: comp-tv
|
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475
|
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476 proc16-vbr:
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477 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
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478 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
|
|
|
479 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
|
|
|
480 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
481 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
|
|
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482 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
|
|
|
483 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
484 # A law input -> ADPCM 16kbit/s -> mu law output
|
|
|
485 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
|
|
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486 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
|
|
|
487 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
488 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
|
|
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489 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
|
|
|
490 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
491 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
|
|
|
492 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
|
|
|
493 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
494 # mu law input -> ADPCM 16kbit/s ->A law output
|
|
|
495 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
|
|
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496 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
|
|
|
497 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
498 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
|
|
|
499 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
|
|
|
500
|
|
|
501 proc24-vbr:
|
|
|
502 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
503 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
|
|
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504 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
|
|
|
505 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
506 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
|
|
|
507 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
|
|
|
508 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
509 # A law input -> ADPCM 24kbit/s -> mu law output
|
|
|
510 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
|
|
|
511 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
|
|
|
512 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
513 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
|
|
|
514 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
|
|
|
515 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
516 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
|
|
|
517 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
|
|
|
518 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
519 # mu law input -> ADPCM 24kbit/s ->A law output
|
|
|
520 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
|
|
|
521 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
|
|
|
522 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
523 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
|
|
|
524 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
|
|
|
525
|
|
|
526 proc32-vbr:
|
|
|
527 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
528 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
|
|
|
529 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
|
|
|
530 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
531 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
|
|
|
532 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
|
|
|
533 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
534 # A law input -> ADPCM 32kbit/s -> mu law output
|
|
|
535 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
|
|
|
536 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
|
|
|
537 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
538 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
|
|
|
539 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
|
|
|
540 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
541 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
|
|
|
542 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
|
|
|
543 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
544 # mu law input -> ADPCM 32kbit/s ->A law output
|
|
|
545 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
|
|
|
546 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
|
|
|
547 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
548 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
|
|
|
549 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
|
|
|
550
|
|
|
551 proc40-vbr:
|
|
|
552 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
553 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
|
|
|
554 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
|
|
|
555 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
556 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
|
|
|
557 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
|
|
|
558 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
559 # A law input -> ADPCM 40kbit/s -> mu law output
|
|
|
560 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
|
|
|
561 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
|
|
|
562 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
563 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
|
|
|
564 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
|
|
|
565 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
566 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
|
|
|
567 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
|
|
|
568 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
569 # mu law input -> ADPCM 40kbit/s ->A law output
|
|
|
570 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
|
|
|
571 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
|
|
|
572 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
573 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
|
|
|
574 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
|
|
|
575
|
|
|
576 # =========================================
|
|
|
577 # Process by batch
|
|
|
578 # =========================================
|
|
|
579 batchtest:
|
|
|
580 batch test-g726
|
|
|
581
|
|
|
582 batchtest-vbr:
|
|
|
583 echo make -f makefile.unx test-vbr | batch
|
