audiostuff: spandsp-0.0.6pre17/src/fsk.c annotate

author	Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date	Fri, 25 Jun 2010 15:50:58 +0200
parents
children

rev	line source
4 26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	1 /*
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	2 * SpanDSP - a series of DSP components for telephony
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	3 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	4 * fsk.c - FSK modem transmit and receive parts
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	5 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	6 * Written by Steve Underwood <steveu@coppice.org>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	7 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	8 * Copyright (C) 2003 Steve Underwood
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	9 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	10 * All rights reserved.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	11 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	12 * This program is free software; you can redistribute it and/or modify
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	13 * it under the terms of the GNU Lesser General Public License version 2.1,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	14 * as published by the Free Software Foundation.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	15 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	16 * This program is distributed in the hope that it will be useful,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	19 * GNU Lesser General Public License for more details.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	20 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	21 * You should have received a copy of the GNU Lesser General Public
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	22 * License along with this program; if not, write to the Free Software
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	24 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	25 * $Id: fsk.c,v 1.60 2009/11/02 13:25:20 steveu Exp $
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	26 */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	27
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	28 /! \file /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	29
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	30 #if defined(HAVE_CONFIG_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	31 #include "config.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	32 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	33
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	34 #include <stdlib.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	35 #include <inttypes.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	36 #include <string.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	37 #if defined(HAVE_TGMATH_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	38 #include <tgmath.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	39 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	40 #if defined(HAVE_MATH_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	41 #include <math.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	42 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	43 #include "floating_fudge.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	44 #include <assert.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	45
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	46 #include "spandsp/telephony.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	47 #include "spandsp/complex.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	48 #include "spandsp/dds.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	49 #include "spandsp/power_meter.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	50 #include "spandsp/async.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	51 #include "spandsp/fsk.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	52
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	53 #include "spandsp/private/fsk.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	54
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	55 const fsk_spec_t preset_fsk_specs[] =
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	56 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	57 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	58 "V21 ch 1",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	59 1080 + 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	60 1080 - 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	61 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	62 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	63 300*100
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	64 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	65 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	66 "V21 ch 2",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	67 1750 + 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	68 1750 - 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	69 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	70 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	71 300*100
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	72 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	73 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	74 "V23 ch 1",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	75 2100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	76 1300,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	77 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	78 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	79 1200*100
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	80 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	81 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	82 "V23 ch 2",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	83 450,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	84 390,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	85 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	86 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	87 75*100
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	88 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	89 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	90 "Bell103 ch 1",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	91 2125 - 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	92 2125 + 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	93 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	94 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	95 300*100
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	96 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	97 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	98 "Bell103 ch 2",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	99 1170 - 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	100 1170 + 100,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	101 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	102 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	103 300*100
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	104 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	105 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	106 "Bell202",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	107 2200,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	108 1200,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	109 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	110 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	111 1200*100
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	112 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	113 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	114 "Weitbrecht 45.45", /* Used for TDD (Telecoms Device for the Deaf) */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	115 1800,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	116 1400,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	117 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	118 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	119 4545
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	120 },
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	121 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	122 "Weitbrecht 50", /* Used for TDD (Telecoms Device for the Deaf) */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	123 1800,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	124 1400,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	125 -14,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	126 -30,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	127 5000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	128 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	129 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	130
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	131 SPAN_DECLARE(int) fsk_tx_restart(fsk_tx_state_t s, const fsk_spec_t spec)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	132 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	133 s->baud_rate = spec->baud_rate;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	134 s->phase_rates[0] = dds_phase_rate((float) spec->freq_zero);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	135 s->phase_rates[1] = dds_phase_rate((float) spec->freq_one);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	136 s->scaling = dds_scaling_dbm0((float) spec->tx_level);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	137 /* Initialise fractional sample baud generation. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	138 s->phase_acc = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	139 s->baud_frac = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	140 s->current_phase_rate = s->phase_rates[1];
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	141
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	142 s->shutdown = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	143 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	144 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	145 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	146
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	147 SPAN_DECLARE(fsk_tx_state_t ) fsk_tx_init(fsk_tx_state_t s,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	148 const fsk_spec_t *spec,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	149 get_bit_func_t get_bit,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	150 void *user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	151 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	152 if (s == NULL)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	153 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	154 if ((s = (fsk_tx_state_t ) malloc(sizeof(s))) == NULL)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	155 return NULL;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	156 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	157 memset(s, 0, sizeof(*s));
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	158
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	159 s->get_bit = get_bit;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	160 s->get_bit_user_data = user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	161 fsk_tx_restart(s, spec);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	162 return s;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	163 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	164 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	165
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	166 SPAN_DECLARE(int) fsk_tx_release(fsk_tx_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	167 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	168 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	169 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	170 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	171
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	172 SPAN_DECLARE(int) fsk_tx_free(fsk_tx_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	173 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	174 free(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	175 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	176 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	177 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	178
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	179 SPAN_DECLARE_NONSTD(int) fsk_tx(fsk_tx_state_t *s, int16_t amp[], int len)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	180 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	181 int sample;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	182 int bit;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	183
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	184 if (s->shutdown)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	185 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	186 /* Make the transitions between 0 and 1 phase coherent, but instantaneous
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	187 jumps. There is currently no interpolation for bauds that end mid-sample.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	188 Mainstream users will not care. Some specialist users might have a problem
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	189 with them, if they care about accurate transition timing. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	190 for (sample = 0; sample < len; sample++)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	191 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	192 if ((s->baud_frac += s->baud_rate) >= SAMPLE_RATE*100)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	193 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	194 s->baud_frac -= SAMPLE_RATE*100;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	195 if ((bit = s->get_bit(s->get_bit_user_data)) == SIG_STATUS_END_OF_DATA)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	196 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	197 if (s->status_handler)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	198 s->status_handler(s->status_user_data, SIG_STATUS_END_OF_DATA);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	199 if (s->status_handler)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	200 s->status_handler(s->status_user_data, SIG_STATUS_SHUTDOWN_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	201 s->shutdown = TRUE;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	202 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	203 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	204 s->current_phase_rate = s->phase_rates[bit & 1];
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	205 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	206 amp[sample] = dds_mod(&(s->phase_acc), s->current_phase_rate, s->scaling, 0);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	207 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	208 return sample;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	209 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	210 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	211
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	212 SPAN_DECLARE(void) fsk_tx_power(fsk_tx_state_t *s, float power)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	213 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	214 s->scaling = dds_scaling_dbm0(power);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	215 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	216 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	217
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	218 SPAN_DECLARE(void) fsk_tx_set_get_bit(fsk_tx_state_t s, get_bit_func_t get_bit, void user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	219 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	220 s->get_bit = get_bit;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	221 s->get_bit_user_data = user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	222 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	223 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	224
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	225 SPAN_DECLARE(void) fsk_tx_set_modem_status_handler(fsk_tx_state_t s, modem_tx_status_func_t handler, void user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	226 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	227 s->status_handler = handler;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	228 s->status_user_data = user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	229 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	230 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	231
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	232 SPAN_DECLARE(void) fsk_rx_signal_cutoff(fsk_rx_state_t *s, float cutoff)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	233 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	234 /* The 6.04 allows for the gain of the DC blocker */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	235 s->carrier_on_power = (int32_t) (power_meter_level_dbm0(cutoff + 2.5f - 6.04f));
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	236 s->carrier_off_power = (int32_t) (power_meter_level_dbm0(cutoff - 2.5f - 6.04f));
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	237 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	238 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	239
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	240 SPAN_DECLARE(float) fsk_rx_signal_power(fsk_rx_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	241 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	242 return power_meter_current_dbm0(&s->power);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	243 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	244 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	245
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	246 SPAN_DECLARE(void) fsk_rx_set_put_bit(fsk_rx_state_t s, put_bit_func_t put_bit, void user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	247 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	248 s->put_bit = put_bit;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	249 s->put_bit_user_data = user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	250 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	251 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	252
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	253 SPAN_DECLARE(void) fsk_rx_set_modem_status_handler(fsk_rx_state_t s, modem_tx_status_func_t handler, void user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	254 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	255 s->status_handler = handler;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	256 s->status_user_data = user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	257 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	258 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	259
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	260 SPAN_DECLARE(int) fsk_rx_restart(fsk_rx_state_t s, const fsk_spec_t spec, int framing_mode)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	261 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	262 int chop;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	263
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	264 s->baud_rate = spec->baud_rate;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	265 s->framing_mode = framing_mode;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	266 fsk_rx_signal_cutoff(s, (float) spec->min_level);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	267
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	268 /* Detect by correlating against the tones we want, over a period
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	269 of one baud. The correlation must be quadrature. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	270
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	271 /* First we need the quadrature tone generators to correlate
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	272 against. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	273 s->phase_rate[0] = dds_phase_rate((float) spec->freq_zero);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	274 s->phase_rate[1] = dds_phase_rate((float) spec->freq_one);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	275 s->phase_acc[0] = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	276 s->phase_acc[1] = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	277 s->last_sample = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	278
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	279 /* The correlation should be over one baud. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	280 s->correlation_span = SAMPLE_RATE*100/spec->baud_rate;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	281 /* But limit it for very slow baud rates, so we do not overflow our
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	282 buffer. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	283 if (s->correlation_span > FSK_MAX_WINDOW_LEN)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	284 s->correlation_span = FSK_MAX_WINDOW_LEN;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	285
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	286 /* We need to scale, to avoid overflow in the correlation. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	287 s->scaling_shift = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	288 chop = s->correlation_span;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	289 while (chop != 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	290 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	291 s->scaling_shift++;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	292 chop >>= 1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	293 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	294
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	295 /* Initialise the baud/bit rate tracking. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	296 s->baud_phase = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	297 s->frame_state = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	298 s->frame_bits = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	299 s->last_bit = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	300
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	301 /* Initialise a power detector, so sense when a signal is present. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	302 power_meter_init(&(s->power), 4);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	303 s->signal_present = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	304 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	305 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	306 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	307
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	308 SPAN_DECLARE(fsk_rx_state_t ) fsk_rx_init(fsk_rx_state_t s,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	309 const fsk_spec_t *spec,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	310 int framing_mode,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	311 put_bit_func_t put_bit,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	312 void *user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	313 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	314 if (s == NULL)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	315 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	316 if ((s = (fsk_rx_state_t ) malloc(sizeof(s))) == NULL)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	317 return NULL;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	318 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	319 memset(s, 0, sizeof(*s));
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	320
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	321 s->put_bit = put_bit;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	322 s->put_bit_user_data = user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	323 fsk_rx_restart(s, spec, framing_mode);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	324 return s;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	325 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	326 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	327
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	328 SPAN_DECLARE(int) fsk_rx_release(fsk_rx_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	329 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	330 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	331 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	332 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	333
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	334 SPAN_DECLARE(int) fsk_rx_free(fsk_rx_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	335 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	336 free(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	337 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	338 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	339 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	340
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	341 static void report_status_change(fsk_rx_state_t *s, int status)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	342 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	343 if (s->status_handler)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	344 s->status_handler(s->status_user_data, status);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	345 else if (s->put_bit)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	346 s->put_bit(s->put_bit_user_data, status);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	347 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	348 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	349
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	350 SPAN_DECLARE_NONSTD(int) fsk_rx(fsk_rx_state_t s, const int16_t amp, int len)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	351 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	352 int buf_ptr;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	353 int baudstate;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	354 int i;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	355 int j;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	356 int16_t x;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	357 int32_t dot;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	358 int32_t sum[2];
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	359 int32_t power;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	360 complexi_t ph;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	361
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	362 buf_ptr = s->buf_ptr;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	363
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	364 for (i = 0; i < len; i++)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	365 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	366 /* The totally asynchronous character to character behaviour of these
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	367 modems, when carrying async. data, seems to force a sample by sample
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	368 approach. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	369 for (j = 0; j < 2; j++)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	370 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	371 s->dot[j].re -= s->window[j][buf_ptr].re;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	372 s->dot[j].im -= s->window[j][buf_ptr].im;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	373
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	374 ph = dds_complexi(&(s->phase_acc[j]), s->phase_rate[j]);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	375 s->window[j][buf_ptr].re = (ph.re*amp[i]) >> s->scaling_shift;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	376 s->window[j][buf_ptr].im = (ph.im*amp[i]) >> s->scaling_shift;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	377
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	378 s->dot[j].re += s->window[j][buf_ptr].re;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	379 s->dot[j].im += s->window[j][buf_ptr].im;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	380
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	381 dot = s->dot[j].re >> 15;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	382 sum[j] = dot*dot;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	383 dot = s->dot[j].im >> 15;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	384 sum[j] += dot*dot;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	385 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	386 /* If there isn't much signal, don't demodulate - it will only produce
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	387 useless junk results. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	388 /* There should be no DC in the signal, but sometimes there is.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	389 We need to measure the power with the DC blocked, but not using
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	390 a slow to respond DC blocker. Use the most elementary HPF. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	391 x = amp[i] >> 1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	392 power = power_meter_update(&(s->power), x - s->last_sample);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	393 s->last_sample = x;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	394 if (s->signal_present)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	395 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	396 /* Look for power below turn-off threshold to turn the carrier off */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	397 if (power < s->carrier_off_power)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	398 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	399 if (--s->signal_present <= 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	400 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	401 /* Count down a short delay, to ensure we push the last
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	402 few bits through the filters before stopping. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	403 report_status_change(s, SIG_STATUS_CARRIER_DOWN);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	404 s->baud_phase = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	405 continue;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	406 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	407 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	408 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	409 else
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	410 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	411 /* Look for power exceeding turn-on threshold to turn the carrier on */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	412 if (power < s->carrier_on_power)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	413 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	414 s->baud_phase = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	415 continue;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	416 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	417 if (s->baud_phase < (s->correlation_span >> 1) - 30)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	418 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	419 s->baud_phase++;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	420 continue;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	421 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	422 s->signal_present = 1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	423 /* Initialise the baud/bit rate tracking. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	424 s->baud_phase = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	425 s->frame_state = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	426 s->frame_bits = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	427 s->last_bit = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	428 report_status_change(s, SIG_STATUS_CARRIER_UP);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	429 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	430 /* Non-coherent FSK demodulation by correlation with the target tones
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	431 over a one baud interval. The slow V.xx specs. are too open ended
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	432 to allow anything fancier to be used. The dot products are calculated
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	433 using a sliding window approach, so the compute load is not that great. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	434
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	435 baudstate = (sum[0] < sum[1]);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	436 switch (s->framing_mode)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	437 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	438 case FSK_FRAME_MODE_SYNC:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	439 /* Synchronous serial operation - e.g. for HDLC */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	440 if (s->last_bit != baudstate)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	441 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	442 /* On a transition we check our timing */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	443 s->last_bit = baudstate;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	444 /* For synchronous use (e.g. HDLC channels in FAX modems), nudge
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	445 the baud phase gently, trying to keep it centred on the bauds. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	446 if (s->baud_phase < (SAMPLE_RATE*50))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	447 s->baud_phase += (s->baud_rate >> 3);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	448 else
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	449 s->baud_phase -= (s->baud_rate >> 3);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	450 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	451 if ((s->baud_phase += s->baud_rate) >= (SAMPLE_RATE*100))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	452 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	453 /* We should be in the middle of a baud now, so report the current
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	454 state as the next bit */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	455 s->baud_phase -= (SAMPLE_RATE*100);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	456 s->put_bit(s->put_bit_user_data, baudstate);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	457 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	458 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	459 case FSK_FRAME_MODE_ASYNC:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	460 /* Fully asynchronous mode */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	461 if (s->last_bit != baudstate)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	462 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	463 /* On a transition we check our timing */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	464 s->last_bit = baudstate;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	465 /* For async. operation, believe transitions completely, and
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	466 sample appropriately. This allows instant start on the first
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	467 transition. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	468 /* We must now be about half way to a sampling point. We do not do
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	469 any fractional sample estimation of the transitions, so this is
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	470 the most accurate baud alignment we can do. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	471 s->baud_phase = SAMPLE_RATE*50;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	472 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	473 if ((s->baud_phase += s->baud_rate) >= (SAMPLE_RATE*100))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	474 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	475 /* We should be in the middle of a baud now, so report the current
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	476 state as the next bit */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	477 s->baud_phase -= (SAMPLE_RATE*100);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	478 s->put_bit(s->put_bit_user_data, baudstate);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	479 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	480 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	481 default:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	482 /* Gather the specified number of bits, with robust checking to ensure reasonable voice immunity.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	483 The first bit should be a start bit (0), and the last bit should be a stop bit (1) */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	484 if (s->frame_state == 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	485 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	486 /* Looking for the start of a zero bit, which hopefully the start of a start bit */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	487 if (baudstate == 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	488 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	489 s->baud_phase = SAMPLE_RATE*(100 - 40)/2;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	490 s->frame_state = -1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	491 s->frame_bits = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	492 s->last_bit = -1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	493 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	494 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	495 else if (s->frame_state == -1)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	496 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	497 /* Look for a continuous zero from the start of the start bit until
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	498 beyond the middle */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	499 if (baudstate != 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	500 {

4

26cd8f1ef0b1 import spandsp-0.0.6pre17