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1 # -----------------------------------------------------------------------------
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2 # GNU-C MSDOS-port makefile for compiling and testing the G.726
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3 # implementation. The executable must be defined by variable G726 below.
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4 # 01.May.94 - Implemented by <simao@cpqd.ansp.br>
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5 # 10.Mar.95 - Compilation and test sequence processing/comparison for
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6 # vbr-g726.c. <simao@ctd.comsat.com>
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7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
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8 # order to perform the (optional) compliance test.
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9 # -----------------------------------------------------------------------------
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10
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11 # ------------------------------------------------
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12 # Choose compileroptions
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13 # ------------------------------------------------
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14 CC_OPT = -I../utl
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15
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16 # ------------------------------------------------
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17 # General purpose symbols
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18 # ------------------------------------------------
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19 G726 = go32 g726demo
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20 VBR = go32 vbr-g726 -q
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21 DIFF = cf -q
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22 RM = -rm
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23
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24 # ------------------------------------------------
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25 # Choose an archiving utility:
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26 # - public domain unzip, or [PC/Unix/VMS]
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27 # - shareware pkunzip [PC only]
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28 # ------------------------------------------------
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29 #UNZIP = pkunzip
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30 UNZIP = unzip -o
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31
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32 # ------------------------------------------------
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33 # File lists
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34 # ------------------------------------------------
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35 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
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36
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37 DEMO_OBJ = g726demo.o g726.o
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38 VBR_OBJ = vbr-g726.o g726.o g711.o
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39
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40 # ------------------------------------------------
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41 # Targets
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42 # ------------------------------------------------
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43 all:: g726demo vbr-g726
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44
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45 anyway: clean all
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46
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47 clean:
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48 $(RM) *.o
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49
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50 cleantest:
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51 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
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52 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
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53
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54 veryclean: clean cleantest
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55 $(RM) g726demo vbr-g726
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56
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57 # -----------------------------------------------------------------------------
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58 # Generic rules
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59 # -----------------------------------------------------------------------------
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60 .c.o:
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61 $(CC) $(CC_OPT) -c $<
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62
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63 # -----------------------------------------------------------------------------
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64 # Specific rules
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65 # -----------------------------------------------------------------------------
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66 vbr-g726: $(VBR_OBJ)
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67 $(CC) -o vbr-g726 $(VBR_OBJ) -lm
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68
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69 g726demo: $(DEMO_OBJ)
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70 $(CC) -o g726demo $(DEMO_OBJ) -lm
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71
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72 g726demo.o: g726demo.c g726.h
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73 $(CC) -c $(CC_OPT) -I../g711 g726demo.c
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74
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75 g726.o: g726.c g726.h
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76 $(CC) -c $(CC_OPT) g726.c
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77
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78 g711.o: ../g711/g711.c
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79 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
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80
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81 vbr-g726.o: vbr-g726.c
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82 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
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83
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84 # ----------------------------------------
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85 # Very simple portability test
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86 # ----------------------------------------
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87 test: test-vbr-quick
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88 proc: proc-vbr-quick
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89 comp: comp-vbr-quick
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90
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91 test-vbr-quick: proc-vbr-quick comp-vbr-quick
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92 proc-vbr-quick: voice.src
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93 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
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94 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
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95 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
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96 comp-vbr-quick: voicevbr.arf
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97 $(DIFF) voicvbra.tst voicevbr.arf
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98 $(DIFF) voicvbrl.tst voicevbr.lrf
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99 $(DIFF) voicvbru.tst voicevbr.urf
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100
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101 voice.src: tst-g726.zip
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102 $(UNZIP) tst-g726.zip voice.src
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103 sb -over voice.src
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104
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105 voicevbr.arf: tst-g726.zip
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106 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
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107 swapover voicevbr.arf voicevbr.lrf voicevbr.urf
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108
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109 # -----------------------------------------------------------------------------
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110 # Test the implementation for g726demo (compliance)
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111 # In the automatic compliance testing, g726demo.c is verified by test-tv
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112 # For vbr-g726.c, no differences should be observed, since both use g726.c,
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113 # and differ only on the demo logic. For full compliance testing of the
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114 # vbr-g726.c program, use test-tv-vbr
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115 # -----------------------------------------------------------------------------
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116 test-tv: proc-tv-fix comp-tv
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117 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
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118 comp-tv-fix: comp-tv
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119 comp-tv: comp16 comp24 comp32 comp40
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120
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121 proc16-fix:
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122 #
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123 # Process ADPCM/ Coder for normal and overload sequences, A law
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124 #
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125 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
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126 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
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127 #
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128 # Process ADPCM/ Decoder for normal and overload sequences, A law
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129 #
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130 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
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131 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
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132 #
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133 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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134 # A law input -> ADPCM 16kbit/s -> mu law output
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135 #
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136 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
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137 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
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138 #
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139 #
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140 # Process ADPCM/ Coder for normal and overload sequences, mu law
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141 #
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142 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
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143 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
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144 #
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145 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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146 #
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147 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
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148 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
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149 #
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150 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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151 # mu law input -> ADPCM 16kbit/s -> A law output
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152 #
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153 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
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154 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
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155 #
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156 #
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157 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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158 #
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159 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
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160 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
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161
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162 comp16:
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163 #
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164 # =================================================================
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165 # COMPARISON OF FILES !
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166 # =================================================================
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167 #
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168 # Compare ADPCM/ Coder for normal and overload sequences, A law
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169 #
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170 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
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171 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
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172 #
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173 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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174 #
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175 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
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176 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
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177 #
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178 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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179 # A law input -> ADPCM x kbit/s -> mu law output
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180 #
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181 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
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182 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
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183 #
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184 #
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185 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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186 #
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187 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
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188 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
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189 #
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190 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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191 #
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192 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
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193 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
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194 #
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195 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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196 # mu law input -> ADPCM x kbit/s -> A law output
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197 #
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198 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
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199 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
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200 #
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201 #
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202 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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203 #
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204 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
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205 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
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206
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207 proc24-fix:
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208 #
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209 #
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210 # Process ADPCM/ Coder for normal and overload sequences, A law
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211 #
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212 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
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213 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
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214 #
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215 # Process ADPCM/ Decoder for normal and overload sequences, A law
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216 #
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217 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
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218 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
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219 #
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220 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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221 # A law input -> ADPCM 24kbit/s -> mu law output
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222 #
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223 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
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224 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
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225 #
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226 #
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227 # Process ADPCM/ Coder for normal and overload sequences, mu law
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228 #
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229 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
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230 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
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231 #
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232 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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233 #
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234 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
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235 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
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236 #
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237 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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238 # mu law input -> ADPCM 24kbit/s -> A law output
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239 #
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240 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
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241 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
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242 #
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243 #
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244 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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245 #
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246 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
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247 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
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248
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249 comp24:
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250 #
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251 # =================================================================
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252 # COMPARISON OF FILES !
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253 # =================================================================
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254 #
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255 # Compare ADPCM/ Coder for normal and overload sequences, A law
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256 #
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257 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
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258 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
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259 #
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260 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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261 #
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262 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
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263 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
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264 #
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265 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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266 # A law input -> ADPCM x kbit/s -> mu law output
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267 #
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268 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
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269 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
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270 #
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271 #
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272 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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273 #
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274 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
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275 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
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276 #
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277 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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278 #
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279 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
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280 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
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281 #
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282 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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283 # mu law input -> ADPCM x kbit/s -> A law output
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284 #
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285 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
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286 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
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287 #
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288 #
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289 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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290 #
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291 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
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292 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
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293
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294 proc32-fix:
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295 #
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296 # Process ADPCM/ Coder for normal and overload sequences, A law
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297 #
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298 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
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299 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
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300 #
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301 # Process ADPCM/ Decoder for normal and overload sequences, A law
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302 #
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303 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
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304 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
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305 #
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306 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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307 # A law input -> ADPCM 32kbit/s -> mu law output
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308 #
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309 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
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310 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
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311 #
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312 #
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313 # Process ADPCM/ Coder for normal and overload sequences, mu law
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314 #
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315 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
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316 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
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317 #
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318 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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319 #
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320 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
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321 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
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322 #
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323 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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324 # mu law input -> ADPCM 32kbit/s -> A law output
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325 #
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326 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
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327 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
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328 #
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329 #
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330 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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331 #
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332 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
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333 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
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334
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335 comp32:
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336 #
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337 # =================================================================
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338 # COMPARISON OF FILES !
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339 # =================================================================
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340 #
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341 # Compare ADPCM/ Coder for normal and overload sequences, A law
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342 #
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343 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
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344 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
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345 #
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346 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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347 #
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348 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
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349 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
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350 #
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351 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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352 # A law input -> ADPCM x kbit/s -> mu law output
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353 #
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354 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
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355 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
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356 #
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357 #
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358 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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359 #
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360 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
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361 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
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362 #
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363 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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364 #
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365 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
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366 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
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367 #
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368 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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369 # mu law input -> ADPCM x kbit/s -> A law output
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370 #
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371 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
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372 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
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373 #
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374 #
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375 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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376 #
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377 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
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378 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
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379
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380 proc40-fix:
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381 #
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382 #
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383 # Process ADPCM/ Coder for normal and overload sequences, A law
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384 #
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385 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
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386 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
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387 #
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388 # Process ADPCM/ Decoder for normal and overload sequences, A law
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389 #
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390 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
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391 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
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392 #
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393 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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394 # A law input -> ADPCM 40kbit/s -> mu law output
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395 #
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396 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
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397 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
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398 #
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399 #
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400 # Process ADPCM/ Coder for normal and overload sequences, mu law
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401 #
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402 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
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403 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
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404 #
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405 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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406 #
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407 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
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408 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
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409 #
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410 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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411 # mu law input -> ADPCM 40kbit/s -> A law output
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412 #
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413 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
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414 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
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415 #
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416 #
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417 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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418 #
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419 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
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420 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
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421
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422 comp40:
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423 #
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424 # =================================================================
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425 # COMPARISON OF FILES !
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426 # =================================================================
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427 #
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428 # Compare ADPCM/ Coder for normal and overload sequences, A law
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429 #
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430 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
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431 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
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432 #
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433 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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434 #
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435 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
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436 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
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437 #
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438 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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439 # A law input -> ADPCM x kbit/s -> mu law output
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440 #
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441 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
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442 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
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443 #
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444 #
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445 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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446 #
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447 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
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448 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
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449 #
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450 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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451 #
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452 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
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453 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
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454 #
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455 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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456 # mu law input -> ADPCM x kbit/s -> A law output
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457 #
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458 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
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459 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
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460 #
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461 #
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462 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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463 #
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464 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
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465 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
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466
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467 #
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468 # -----------------------------------------------------------------------------
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469 # Test the implementation for vbr-g726 (compliance)
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470 # -----------------------------------------------------------------------------
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471 test-tv-vbr: proc-tv-vbr comp-tv
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472 proc-tv-vbr: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
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473 comp-vbr-tv: comp-tv
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474
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475 proc16-vbr:
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476 # Process ADPCM/ Coder for normal and overload sequences, A law
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477 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
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478 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
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479 # Process ADPCM/ Decoder for normal and overload sequences, A law
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480 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
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481 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
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482 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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483 # A law input -> ADPCM 16kbit/s -> mu law output
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484 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
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485 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
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486 # Process ADPCM/ Coder for normal and overload sequences, mu law
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487 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
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488 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
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489 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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490 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
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491 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
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492 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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493 # mu law input -> ADPCM 16kbit/s ->A law output
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494 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
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495 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
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496 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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497 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
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498 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
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499
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500 proc24-vbr:
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501 # Process ADPCM/ Coder for normal and overload sequences, A law
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502 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
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503 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
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504 # Process ADPCM/ Decoder for normal and overload sequences, A law
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505 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
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506 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
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507 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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508 # A law input -> ADPCM 24kbit/s -> mu law output
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509 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
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510 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
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511 # Process ADPCM/ Coder for normal and overload sequences, mu law
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512 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
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513 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
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514 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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515 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
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516 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
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517 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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518 # mu law input -> ADPCM 24kbit/s ->A law output
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519 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
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520 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
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521 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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522 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
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523 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
|
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524
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525 proc32-vbr:
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526 # Process ADPCM/ Coder for normal and overload sequences, A law
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|
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527 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
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528 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
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|
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529 # Process ADPCM/ Decoder for normal and overload sequences, A law
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|
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530 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
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531 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
|
|
|
532 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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|
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533 # A law input -> ADPCM 32kbit/s -> mu law output
|
|
|
534 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
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|
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535 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
|
|
|
536 # Process ADPCM/ Coder for normal and overload sequences, mu law
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|
|
537 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
|
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538 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
|
|
|
539 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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|
|
540 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
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|
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541 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
|
|
|
542 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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|
|
543 # mu law input -> ADPCM 32kbit/s ->A law output
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|
|
544 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
|
|
|
545 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
|
|
|
546 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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|
|
547 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
|
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548 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
|
|
|
549
|
|
|
550 proc40-vbr:
|
|
|
551 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
552 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
|
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553 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
|
|
|
554 # Process ADPCM/ Decoder for normal and overload sequences, A law
|
|
|
555 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
|
|
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556 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
|
|
|
557 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
558 # A law input -> ADPCM 40kbit/s -> mu law output
|
|
|
559 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
|
|
|
560 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
|
|
|
561 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
562 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
|
|
|
563 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
|
|
|
564 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
565 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
|
|
|
566 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
|
|
|
567 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
568 # mu law input -> ADPCM 40kbit/s ->A law output
|
|
|
569 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
|
|
|
570 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
|
|
|
571 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
572 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
|
|
|
573 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
|
|
|
574
|
|
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575
|
|
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576
|
