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1 # -----------------------------------------------------------------------------
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2 # Borland tcc/bcc makefile for compiling and testing the G.726
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3 # implementation. The executable must be defined by variable G726 below.
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4 # 01.May.94 - Implemented by <simao@cpqd.ansp.br>
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5 # 10.Mar.95 - Compilation and test sequence processing/comparison for
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6 # vbr-g726.c. <simao@ctd.comsat.com>
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7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
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8 # order to perform the (optional) compliance test.
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9 # -----------------------------------------------------------------------------
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10
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11 # ------------------------------------------------
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12 # Choose compiler/options.
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13 # ------------------------------------------------
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14 #CC = bcc
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15 CC = tcc
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16 CC_OPT = -I../utl
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17
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18 # ------------------------------------------------
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19 # General purpose symbols
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20 # ------------------------------------------------
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21 G726 = g726demo
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22 VBR = vbr-g726 -q
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23 DIFF = cf -q
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24 RM = -rm -f
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25
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26 # ------------------------------------------------
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27 # Choose an archiving utility:
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28 # - public domain unzip, or [PC/Unix/VMS]
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29 # - shareware pkunzip [PC only]
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30 # ------------------------------------------------
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31 #UNZIP = pkunzip
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32 UNZIP = unzip -o
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33
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34 # ------------------------------------------------
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35 # File lists
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36 # ------------------------------------------------
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37 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
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38
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39 DEMO_OBJ = g726demo.obj g726.obj
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40 VBR_OBJ = vbr-g726.obj g726.obj g711.obj
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41
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42 # ------------------------------------------------
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43 # Targets
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44 # ------------------------------------------------
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45 all: g726demo vbr-g726
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46
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47 anyway: clean all
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48
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49 clean:
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50 $(RM) *.obj
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51
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52 cleantest:
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53 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
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54 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
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55
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56 veryclean: clean cleantest
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57 $(RM) g726demo.exe vbr-g726.exe
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58
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59 # -----------------------------------------------------------------------------
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60 # Generic rules
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61 # -----------------------------------------------------------------------------
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62 .c.obj:
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63 $(CC) $(CC_OPT) -c $<
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64
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65 # -----------------------------------------------------------------------------
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66 # Specific rules
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67 # -----------------------------------------------------------------------------
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68 vbr-g726: vbr-g726.exe
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69 g726demo: g726demo.exe
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70
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71 vbr-g726.exe: $(VBR_OBJ)
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72 $(CC) -evbr-g726 $(VBR_OBJ)
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73
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74 g726demo.exe: $(DEMO_OBJ)
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75 $(CC) -eg726demo $(DEMO_OBJ)
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76
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77 g726demo.obj: g726demo.c g726.h
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78 $(CC) $(CC_OPT) -c -I../g711 g726demo.c
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79
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80 g726.obj: g726.c g726.h
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81 $(CC) -c $(CC_OPT) g726.c
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82
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83 g711.obj: ../g711/g711.c
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84 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
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85
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86 vbr-g726.obj: vbr-g726.c
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87 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
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88
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89 # ----------------------------------------
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90 # Very simple portability test
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91 # ----------------------------------------
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92 test: test-vbr-quick
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93 proc: proc-vbr-quick
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94 comp: comp-vbr-quick
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95
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96 test-vbr-quick: proc-vbr-quick comp-vbr-quick
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97 proc-vbr-quick: voice.src
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98 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
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99 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
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100 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
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101 comp-vbr-quick: voicevbr.arf
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102 $(DIFF) voicvbra.tst voicevbr.arf
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103 $(DIFF) voicvbrl.tst voicevbr.lrf
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104 $(DIFF) voicvbru.tst voicevbr.urf
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105
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106 voice.src: tst-g726.zip
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107 $(UNZIP) tst-g726.zip voice.src
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108 sb -over voice.src
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109
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110 voicevbr.arf: tst-g726.zip
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111 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
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112 swapover voicevbr.arf voicevbr.lrf voicevbr.urf
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113
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114 # -----------------------------------------------------------------------------
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115 # Test the implementation for g726demo (compliance)
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116 # In the automatic compliance testing, g726demo.c is verified by test-tv
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117 # For vbr-g726.c, no differences should be observed, since both use g726.c,
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118 # and differ only on the demo logic. For full compliance testing of the
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119 # vbr-g726.c program, use test-tv-vbr
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120 # -----------------------------------------------------------------------------
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121 test-tv: proc-tv-fix comp-tv
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122 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
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123 comp-tv-fix: comp-tv
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124 comp-tv: comp16 comp24 comp32 comp40
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125
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126 proc16-fix:
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127 #
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128 # Process ADPCM/ Coder for normal and overload sequences, A law
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129 #
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130 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
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131 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
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132 #
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133 # Process ADPCM/ Decoder for normal and overload sequences, A law
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134 #
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135 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
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136 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
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137 #
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138 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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139 # A law input -> ADPCM 16kbit/s -> mu law output
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140 #
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141 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
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142 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
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143 #
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144 #
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145 # Process ADPCM/ Coder for normal and overload sequences, mu law
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146 #
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147 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
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148 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
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149 #
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150 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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151 #
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152 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
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153 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
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154 #
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155 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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156 # mu law input -> ADPCM 16kbit/s -> A law output
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157 #
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158 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
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159 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
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160 #
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161 #
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162 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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163 #
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164 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
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165 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
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166
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167 comp16:
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168 #
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169 # =================================================================
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170 # COMPARISON OF FILES !
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171 # =================================================================
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172 #
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173 # Compare ADPCM/ Coder for normal and overload sequences, A law
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174 #
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175 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
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176 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
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177 #
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178 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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179 #
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180 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
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181 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
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182 #
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183 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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184 # A law input -> ADPCM x kbit/s -> mu law output
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185 #
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186 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
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187 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
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188 #
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189 #
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190 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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191 #
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192 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
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193 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
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194 #
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195 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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196 #
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197 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
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198 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
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199 #
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200 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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201 # mu law input -> ADPCM x kbit/s -> A law output
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202 #
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203 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
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204 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
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205 #
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206 #
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207 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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208 #
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209 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
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210 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
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211
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212 proc24-fix:
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213 #
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214 #
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215 # Process ADPCM/ Coder for normal and overload sequences, A law
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216 #
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217 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
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218 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
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219 #
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220 # Process ADPCM/ Decoder for normal and overload sequences, A law
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221 #
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222 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
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223 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
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224 #
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225 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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226 # A law input -> ADPCM 24kbit/s -> mu law output
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227 #
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228 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
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229 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
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230 #
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231 #
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232 # Process ADPCM/ Coder for normal and overload sequences, mu law
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233 #
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234 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
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235 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
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236 #
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237 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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238 #
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239 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
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240 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
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241 #
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242 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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243 # mu law input -> ADPCM 24kbit/s -> A law output
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244 #
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245 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
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246 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
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247 #
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248 #
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249 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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250 #
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251 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
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252 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
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253
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254 comp24:
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255 #
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256 # =================================================================
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257 # COMPARISON OF FILES !
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258 # =================================================================
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259 #
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260 # Compare ADPCM/ Coder for normal and overload sequences, A law
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261 #
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262 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
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263 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
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264 #
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265 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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266 #
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267 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
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268 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
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269 #
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270 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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271 # A law input -> ADPCM x kbit/s -> mu law output
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272 #
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273 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
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274 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
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275 #
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276 #
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277 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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278 #
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279 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
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280 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
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281 #
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282 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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283 #
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284 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
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285 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
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286 #
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287 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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288 # mu law input -> ADPCM x kbit/s -> A law output
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289 #
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290 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
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291 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
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292 #
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293 #
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294 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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295 #
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296 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
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297 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
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298
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299 proc32-fix:
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300 #
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301 # Process ADPCM/ Coder for normal and overload sequences, A law
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302 #
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303 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
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304 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
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305 #
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306 # Process ADPCM/ Decoder for normal and overload sequences, A law
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307 #
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308 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
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309 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
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310 #
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311 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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312 # A law input -> ADPCM 32kbit/s -> mu law output
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313 #
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314 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
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315 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
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316 #
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317 #
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318 # Process ADPCM/ Coder for normal and overload sequences, mu law
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319 #
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320 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
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321 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
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322 #
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323 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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324 #
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325 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
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326 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
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327 #
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328 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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329 # mu law input -> ADPCM 32kbit/s -> A law output
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330 #
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331 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
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332 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
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333 #
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334 #
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335 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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336 #
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337 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
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338 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
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339
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340 comp32:
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341 #
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342 # =================================================================
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343 # COMPARISON OF FILES !
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344 # =================================================================
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345 #
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346 # Compare ADPCM/ Coder for normal and overload sequences, A law
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347 #
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348 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
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349 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
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350 #
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351 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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352 #
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353 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
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354 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
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355 #
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356 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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357 # A law input -> ADPCM x kbit/s -> mu law output
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358 #
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359 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
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360 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
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361 #
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362 #
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363 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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364 #
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365 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
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366 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
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367 #
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368 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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369 #
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370 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
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371 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
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372 #
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373 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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374 # mu law input -> ADPCM x kbit/s -> A law output
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375 #
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376 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
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377 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
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378 #
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379 #
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380 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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381 #
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382 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
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383 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
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384
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385 proc40-fix:
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386 #
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387 #
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388 # Process ADPCM/ Coder for normal and overload sequences, A law
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389 #
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390 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
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391 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
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392 #
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393 # Process ADPCM/ Decoder for normal and overload sequences, A law
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394 #
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395 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
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396 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
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397 #
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398 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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399 # A law input -> ADPCM 40kbit/s -> mu law output
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400 #
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401 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
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402 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
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403 #
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404 #
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405 # Process ADPCM/ Coder for normal and overload sequences, mu law
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406 #
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407 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
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408 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
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409 #
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410 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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411 #
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412 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
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413 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
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414 #
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415 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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416 # mu law input -> ADPCM 40kbit/s -> A law output
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417 #
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418 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
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419 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
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420 #
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421 #
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422 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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423 #
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424 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
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425 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
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426
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427 comp40:
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428 #
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429 # =================================================================
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430 # COMPARISON OF FILES !
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431 # =================================================================
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432 #
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433 # Compare ADPCM/ Coder for normal and overload sequences, A law
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434 #
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435 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
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436 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
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437 #
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438 # Compare ADPCM/ Decoder for normal and overload sequences, A law
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439 #
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440 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
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441 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
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442 #
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443 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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444 # A law input -> ADPCM x kbit/s -> mu law output
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445 #
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446 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
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447 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
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448 #
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449 #
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450 # Compare ADPCM/ Coder for normal and overload sequences, mu law
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451 #
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452 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
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453 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
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454 #
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455 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
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456 #
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457 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
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458 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
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459 #
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460 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
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461 # mu law input -> ADPCM x kbit/s -> A law output
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462 #
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463 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
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464 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
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465 #
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466 #
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467 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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468 #
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469 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
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470 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
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471
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472
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473 # -----------------------------------------------------------------------------
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474 # Test the implementation for vbr-g726 (compliance)
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475 # -----------------------------------------------------------------------------
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476 test-vbr-tv: proc-vbr-tv comp-tv
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477 proc-vbr-tv: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
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478 comp-vbr-tv: comp-tv
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479
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480 proc16-vbr:
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481 # Process ADPCM/ Coder for normal and overload sequences, A law
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482 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
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483 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
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484 # Process ADPCM/ Decoder for normal and overload sequences, A law
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485 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
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486 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
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487 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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488 # A law input -> ADPCM 16kbit/s -> mu law output
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489 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
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490 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
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491 # Process ADPCM/ Coder for normal and overload sequences, mu law
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492 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
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493 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
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494 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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495 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
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496 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
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497 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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498 # mu law input -> ADPCM 16kbit/s ->A law output
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499 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
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500 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
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501 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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502 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
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503 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
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504
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505 proc24-vbr:
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506 # Process ADPCM/ Coder for normal and overload sequences, A law
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507 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
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508 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
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509 # Process ADPCM/ Decoder for normal and overload sequences, A law
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510 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
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511 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
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|
|
512 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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513 # A law input -> ADPCM 24kbit/s -> mu law output
|
|
|
514 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
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|
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515 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
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516 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
517 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
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518 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
|
|
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519 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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520 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
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521 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
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|
|
522 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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523 # mu law input -> ADPCM 24kbit/s ->A law output
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|
|
524 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
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525 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
|
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|
526 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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|
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527 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
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528 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
|
|
|
529
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530 proc32-vbr:
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531 # Process ADPCM/ Coder for normal and overload sequences, A law
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|
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532 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
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|
533 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
|
|
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534 # Process ADPCM/ Decoder for normal and overload sequences, A law
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|
|
535 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
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536 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
|
|
|
537 # Process ADPCM/ Cross-decoder for normal and overload sequences,
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|
|
538 # A law input -> ADPCM 32kbit/s -> mu law output
|
|
|
539 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
|
|
|
540 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
|
|
|
541 # Process ADPCM/ Coder for normal and overload sequences, mu law
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|
|
542 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
|
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543 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
|
|
|
544 # Process ADPCM/ Decoder for normal and overload sequences, mu law
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545 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
|
|
|
546 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
|
|
|
547 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
548 # mu law input -> ADPCM 32kbit/s ->A law output
|
|
|
549 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
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550 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
|
|
|
551 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
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|
|
552 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
|
|
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553 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
|
|
|
554
|
|
|
555 proc40-vbr:
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|
556 # Process ADPCM/ Coder for normal and overload sequences, A law
|
|
|
557 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
|
|
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558 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
|
|
|
559 # Process ADPCM/ Decoder for normal and overload sequences, A law
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|
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560 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
|
|
|
561 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
|
|
|
562 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
563 # A law input -> ADPCM 40kbit/s -> mu law output
|
|
|
564 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
|
|
|
565 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
|
|
|
566 # Process ADPCM/ Coder for normal and overload sequences, mu law
|
|
|
567 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
|
|
|
568 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
|
|
|
569 # Process ADPCM/ Decoder for normal and overload sequences, mu law
|
|
|
570 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
|
|
|
571 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
|
|
|
572 # Process ADPCM/ Cross-decoder for normal and overload sequences,
|
|
|
573 # mu law input -> ADPCM 40kbit/s ->A law output
|
|
|
574 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
|
|
|
575 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
|
|
|
576 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
|
|
|
577 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
|
|
|
578 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
|
|
|
579
|
|
|
580
|
