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comparison intercom/g726/makefile.cl @ 2:13be24d74cd2

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import intercom-0.4.1
author Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date Fri, 25 Jun 2010 09:57:52 +0200
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1:9cadc470e3da 2:13be24d74cd2
1 #-----------------------------------------------------------------------------
2 # MS Visual C makefile for compiling and testing the G.726
3 # implementation.
4 # The executable must be defined by variable G726 below.
5 # History:
6 # 31.Jan.2000 - Implemented by <simao.campos@labs.comsat.com>
7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
8 # order to perform the (optional) compliance test.
9 #-----------------------------------------------------------------------------
10
11 # ------------------------------------------------
12 # Choose compiler.
13 # ------------------------------------------------
14 CC=cl
15 CC_OPT = -I../utl /Yd /DEBUG
16
17 # ------------------------------------------------
18 # General purpose symbols
19 # ------------------------------------------------
20 G726 = g726demo
21 VBR = vbr-g726 -q
22 DIFF = cf -q
23 RM=rm -f
24
25 # ------------------------------------------------
26 # Choose an archiving utility:
27 # - public domain unzip, or [PC/Unix/VMS]
28 # - shareware pkunzip [PC only]
29 # ------------------------------------------------
30 #UNZIP = pkunzip
31 UNZIP = unzip -o
32
33 # ------------------------------------------------
34 # File lists
35 # ------------------------------------------------
36 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
37
38 DEMO_OBJ = g726demo.obj g726.obj
39 VBR_OBJ = vbr-g726.obj g726.obj g711.obj
40
41 # ------------------------------------------------
42 # Targets
43 # ------------------------------------------------
44 all:: g726demo vbr-g726
45
46 anyway: clean all
47
48 clean:
49 $(RM) *.obj
50
51 cleantest:
52 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
53 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
54
55 veryclean: clean cleantest
56 $(RM) g726demo.exe vbr-g726.exe
57
58 # -----------------------------------------------------------------------------
59 # Generic rules
60 # -----------------------------------------------------------------------------
61 .c.obj:
62 $(CC) $(CC_OPT) -c $<
63
64 # -----------------------------------------------------------------------------
65 # Specific rules
66 # -----------------------------------------------------------------------------
67 vbr-g726: vbr-g726.exe
68 g726demo: g726demo.exe
69 vbr-g726.exe: $(VBR_OBJ)
70 $(CC) -o vbr-g726 $(CC_OPT) $(VBR_OBJ)
71
72 g726demo.exe: $(DEMO_OBJ)
73 $(CC) -o g726demo $(CC_OPT) $(DEMO_OBJ)
74
75 g726demo.obj: g726demo.c
76 $(CC) -c $(CC_OPT) -I../g711 g726demo.c
77
78 g726.obj: g726.c
79 $(CC) -c $(CC_OPT) g726.c
80
81 g711.obj: ../g711/g711.c
82 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
83
84 vbr-g726.obj: vbr-g726.c
85 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
86
87 # ----------------------------------------
88 # Very simple portability test
89 # ----------------------------------------
90 test: test-vbr-quick
91 proc: proc-vbr-quick
92 comp: comp-vbr-quick
93
94 test-vbr-quick: proc-vbr-quick comp-vbr-quick
95 proc-vbr-quick: voice.src
96 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
97 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
98 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
99 comp-vbr-quick: voicevbr.arf
100 $(DIFF) voicvbra.tst voicevbr.arf
101 $(DIFF) voicvbrl.tst voicevbr.lrf
102 $(DIFF) voicvbru.tst voicevbr.urf
103
104 voice.src: tst-g726.zip
105 $(UNZIP) tst-g726.zip voice.src
106 sb -over voice.src
107
108 voicevbr.arf: tst-g726.zip
109 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
110 swapover voicevbr.arf voicevbr.lrf voicevbr.urf
111
112 # -----------------------------------------------------------------------------
113 # Test the implementation for g726demo (compliance)
114 # In the automatic compliance testing, g726demo.c is verified by test-tv
115 # For vbr-g726.c, no differences should be observed, since both use g726.c,
116 # and differ only on the demo logic. For full compliance testing of the
117 # vbr-g726.c program, use test-tv-vbr
118 # -----------------------------------------------------------------------------
119 test-tv: proc-tv-fix comp-tv
120 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
121 comp-tv-fix: comp-tv
122 comp-tv: comp16 comp24 comp32 comp40
123
124 proc16-fix:
125 #
126 # Process ADPCM/ Coder for normal and overload sequences, A law
127 #
128 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
129 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
130 #
131 # Process ADPCM/ Decoder for normal and overload sequences, A law
132 #
133 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
134 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
135 #
136 # Process ADPCM/ Cross-decoder for normal and overload sequences,
137 # A law input -> ADPCM 16kbit/s -> mu law output
138 #
139 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
140 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
141 #
142 #
143 # Process ADPCM/ Coder for normal and overload sequences, mu law
144 #
145 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
146 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
147 #
148 # Process ADPCM/ Decoder for normal and overload sequences, mu law
149 #
150 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
151 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
152 #
153 # Process ADPCM/ Cross-decoder for normal and overload sequences,
154 # mu law input -> ADPCM 16kbit/s -> A law output
155 #
156 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
157 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
158 #
159 #
160 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
161 #
162 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
163 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
164
165 comp16:
166 #
167 # =================================================================
168 # COMPARISON OF FILES !
169 # =================================================================
170 #
171 # Compare ADPCM/ Coder for normal and overload sequences, A law
172 #
173 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
174 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
175 #
176 # Compare ADPCM/ Decoder for normal and overload sequences, A law
177 #
178 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
179 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
180 #
181 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
182 # A law input -> ADPCM x kbit/s -> mu law output
183 #
184 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
185 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
186 #
187 #
188 # Compare ADPCM/ Coder for normal and overload sequences, mu law
189 #
190 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
191 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
192 #
193 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
194 #
195 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
196 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
197 #
198 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
199 # mu law input -> ADPCM x kbit/s -> A law output
200 #
201 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
202 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
203 #
204 #
205 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
206 #
207 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
208 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
209
210 proc24-fix:
211 #
212 #
213 # Process ADPCM/ Coder for normal and overload sequences, A law
214 #
215 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
216 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
217 #
218 # Process ADPCM/ Decoder for normal and overload sequences, A law
219 #
220 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
221 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
222 #
223 # Process ADPCM/ Cross-decoder for normal and overload sequences,
224 # A law input -> ADPCM 24kbit/s -> mu law output
225 #
226 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
227 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
228 #
229 #
230 # Process ADPCM/ Coder for normal and overload sequences, mu law
231 #
232 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
233 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
234 #
235 # Process ADPCM/ Decoder for normal and overload sequences, mu law
236 #
237 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
238 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
239 #
240 # Process ADPCM/ Cross-decoder for normal and overload sequences,
241 # mu law input -> ADPCM 24kbit/s -> A law output
242 #
243 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
244 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
245 #
246 #
247 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
248 #
249 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
250 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
251
252 comp24:
253 #
254 # =================================================================
255 # COMPARISON OF FILES !
256 # =================================================================
257 #
258 # Compare ADPCM/ Coder for normal and overload sequences, A law
259 #
260 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
261 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
262 #
263 # Compare ADPCM/ Decoder for normal and overload sequences, A law
264 #
265 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
266 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
267 #
268 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
269 # A law input -> ADPCM x kbit/s -> mu law output
270 #
271 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
272 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
273 #
274 #
275 # Compare ADPCM/ Coder for normal and overload sequences, mu law
276 #
277 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
278 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
279 #
280 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
281 #
282 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
283 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
284 #
285 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
286 # mu law input -> ADPCM x kbit/s -> A law output
287 #
288 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
289 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
290 #
291 #
292 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
293 #
294 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
295 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
296
297 proc32-fix:
298 #
299 # Process ADPCM/ Coder for normal and overload sequences, A law
300 #
301 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
302 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
303 #
304 # Process ADPCM/ Decoder for normal and overload sequences, A law
305 #
306 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
307 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
308 #
309 # Process ADPCM/ Cross-decoder for normal and overload sequences,
310 # A law input -> ADPCM 32kbit/s -> mu law output
311 #
312 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
313 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
314 #
315 #
316 # Process ADPCM/ Coder for normal and overload sequences, mu law
317 #
318 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
319 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
320 #
321 # Process ADPCM/ Decoder for normal and overload sequences, mu law
322 #
323 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
324 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
325 #
326 # Process ADPCM/ Cross-decoder for normal and overload sequences,
327 # mu law input -> ADPCM 32kbit/s -> A law output
328 #
329 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
330 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
331 #
332 #
333 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
334 #
335 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
336 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
337
338 comp32:
339 #
340 # =================================================================
341 # COMPARISON OF FILES !
342 # =================================================================
343 #
344 # Compare ADPCM/ Coder for normal and overload sequences, A law
345 #
346 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
347 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
348 #
349 # Compare ADPCM/ Decoder for normal and overload sequences, A law
350 #
351 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
352 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
353 #
354 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
355 # A law input -> ADPCM x kbit/s -> mu law output
356 #
357 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
358 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
359 #
360 #
361 # Compare ADPCM/ Coder for normal and overload sequences, mu law
362 #
363 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
364 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
365 #
366 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
367 #
368 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
369 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
370 #
371 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
372 # mu law input -> ADPCM x kbit/s -> A law output
373 #
374 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
375 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
376 #
377 #
378 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
379 #
380 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
381 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
382
383 proc40-fix:
384 #
385 #
386 # Process ADPCM/ Coder for normal and overload sequences, A law
387 #
388 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
389 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
390 #
391 # Process ADPCM/ Decoder for normal and overload sequences, A law
392 #
393 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
394 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
395 #
396 # Process ADPCM/ Cross-decoder for normal and overload sequences,
397 # A law input -> ADPCM 40kbit/s -> mu law output
398 #
399 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
400 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
401 #
402 #
403 # Process ADPCM/ Coder for normal and overload sequences, mu law
404 #
405 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
406 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
407 #
408 # Process ADPCM/ Decoder for normal and overload sequences, mu law
409 #
410 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
411 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
412 #
413 # Process ADPCM/ Cross-decoder for normal and overload sequences,
414 # mu law input -> ADPCM 40kbit/s -> A law output
415 #
416 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
417 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
418 #
419 #
420 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
421 #
422 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
423 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
424
425 comp40:
426 #
427 # =================================================================
428 # COMPARISON OF FILES !
429 # =================================================================
430 #
431 # Compare ADPCM/ Coder for normal and overload sequences, A law
432 #
433 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
434 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
435 #
436 # Compare ADPCM/ Decoder for normal and overload sequences, A law
437 #
438 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
439 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
440 #
441 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
442 # A law input -> ADPCM x kbit/s -> mu law output
443 #
444 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
445 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
446 #
447 #
448 # Compare ADPCM/ Coder for normal and overload sequences, mu law
449 #
450 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
451 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
452 #
453 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
454 #
455 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
456 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
457 #
458 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
459 # mu law input -> ADPCM x kbit/s -> A law output
460 #
461 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
462 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
463 #
464 #
465 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
466 #
467 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
468 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
469
470 #
471 # ----------------------------------------------------------------------------
472 # Test the implementation for vbr-g726 (compliance)
473 # ----------------------------------------------------------------------------
474 test-tv-vbr: proc-tv-vbr comp-tv
475 proc-tv-vbr: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
476 comp-vbr-tv: comp-tv
477
478 proc16-vbr:
479 # Process ADPCM/ Coder for normal and overload sequences, A law
480 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
481 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
482 # Process ADPCM/ Decoder for normal and overload sequences, A law
483 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
484 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
485 # Process ADPCM/ Cross-decoder for normal and overload sequences,
486 # A law input -> ADPCM 16kbit/s -> mu law output
487 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
488 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
489 # Process ADPCM/ Coder for normal and overload sequences, mu law
490 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
491 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
492 # Process ADPCM/ Decoder for normal and overload sequences, mu law
493 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
494 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
495 # Process ADPCM/ Cross-decoder for normal and overload sequences,
496 # mu law input -> ADPCM 16kbit/s ->A law output
497 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
498 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
499 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
500 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
501 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
502
503 proc24-vbr:
504 # Process ADPCM/ Coder for normal and overload sequences, A law
505 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
506 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
507 # Process ADPCM/ Decoder for normal and overload sequences, A law
508 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
509 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
510 # Process ADPCM/ Cross-decoder for normal and overload sequences,
511 # A law input -> ADPCM 24kbit/s -> mu law output
512 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
513 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
514 # Process ADPCM/ Coder for normal and overload sequences, mu law
515 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
516 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
517 # Process ADPCM/ Decoder for normal and overload sequences, mu law
518 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
519 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
520 # Process ADPCM/ Cross-decoder for normal and overload sequences,
521 # mu law input -> ADPCM 24kbit/s ->A law output
522 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
523 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
524 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
525 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
526 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
527
528 proc32-vbr:
529 # Process ADPCM/ Coder for normal and overload sequences, A law
530 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
531 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
532 # Process ADPCM/ Decoder for normal and overload sequences, A law
533 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
534 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
535 # Process ADPCM/ Cross-decoder for normal and overload sequences,
536 # A law input -> ADPCM 32kbit/s -> mu law output
537 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
538 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
539 # Process ADPCM/ Coder for normal and overload sequences, mu law
540 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
541 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
542 # Process ADPCM/ Decoder for normal and overload sequences, mu law
543 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
544 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
545 # Process ADPCM/ Cross-decoder for normal and overload sequences,
546 # mu law input -> ADPCM 32kbit/s ->A law output
547 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
548 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
549 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
550 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
551 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
552
553 proc40-vbr:
554 # Process ADPCM/ Coder for normal and overload sequences, A law
555 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
556 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
557 # Process ADPCM/ Decoder for normal and overload sequences, A law
558 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
559 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
560 # Process ADPCM/ Cross-decoder for normal and overload sequences,
561 # A law input -> ADPCM 40kbit/s -> mu law output
562 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
563 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
564 # Process ADPCM/ Coder for normal and overload sequences, mu law
565 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
566 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
567 # Process ADPCM/ Decoder for normal and overload sequences, mu law
568 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
569 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
570 # Process ADPCM/ Cross-decoder for normal and overload sequences,
571 # mu law input -> ADPCM 40kbit/s ->A law output
572 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
573 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
574 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
575 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
576 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
577
578 # =========================================
579 # Process by batch
580 # =========================================
581 batchtest:
582 batch test-g726
583
584 batchtest-vbr:
585 echo make -f makefile.unx test-vbr | batch

Repositories maintained by Peter Meerwald, pmeerw@pmeerw.net.