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comparison intercom/g726/makefile.djc @ 2:13be24d74cd2

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import intercom-0.4.1
author Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date Fri, 25 Jun 2010 09:57:52 +0200
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1:9cadc470e3da 2:13be24d74cd2
1 # -----------------------------------------------------------------------------
2 # GNU-C MSDOS-port makefile for compiling and testing the G.726
3 # implementation. The executable must be defined by variable G726 below.
4 # 01.May.94 - Implemented by <simao@cpqd.ansp.br>
5 # 10.Mar.95 - Compilation and test sequence processing/comparison for
6 # vbr-g726.c. <simao@ctd.comsat.com>
7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
8 # order to perform the (optional) compliance test.
9 # -----------------------------------------------------------------------------
10
11 # ------------------------------------------------
12 # Choose compileroptions
13 # ------------------------------------------------
14 CC_OPT = -I../utl
15
16 # ------------------------------------------------
17 # General purpose symbols
18 # ------------------------------------------------
19 G726 = go32 g726demo
20 VBR = go32 vbr-g726 -q
21 DIFF = cf -q
22 RM = -rm
23
24 # ------------------------------------------------
25 # Choose an archiving utility:
26 # - public domain unzip, or [PC/Unix/VMS]
27 # - shareware pkunzip [PC only]
28 # ------------------------------------------------
29 #UNZIP = pkunzip
30 UNZIP = unzip -o
31
32 # ------------------------------------------------
33 # File lists
34 # ------------------------------------------------
35 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
36
37 DEMO_OBJ = g726demo.o g726.o
38 VBR_OBJ = vbr-g726.o g726.o g711.o
39
40 # ------------------------------------------------
41 # Targets
42 # ------------------------------------------------
43 all:: g726demo vbr-g726
44
45 anyway: clean all
46
47 clean:
48 $(RM) *.o
49
50 cleantest:
51 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
52 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
53
54 veryclean: clean cleantest
55 $(RM) g726demo vbr-g726
56
57 # -----------------------------------------------------------------------------
58 # Generic rules
59 # -----------------------------------------------------------------------------
60 .c.o:
61 $(CC) $(CC_OPT) -c $<
62
63 # -----------------------------------------------------------------------------
64 # Specific rules
65 # -----------------------------------------------------------------------------
66 vbr-g726: $(VBR_OBJ)
67 $(CC) -o vbr-g726 $(VBR_OBJ) -lm
68
69 g726demo: $(DEMO_OBJ)
70 $(CC) -o g726demo $(DEMO_OBJ) -lm
71
72 g726demo.o: g726demo.c g726.h
73 $(CC) -c $(CC_OPT) -I../g711 g726demo.c
74
75 g726.o: g726.c g726.h
76 $(CC) -c $(CC_OPT) g726.c
77
78 g711.o: ../g711/g711.c
79 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
80
81 vbr-g726.o: vbr-g726.c
82 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
83
84 # ----------------------------------------
85 # Very simple portability test
86 # ----------------------------------------
87 test: test-vbr-quick
88 proc: proc-vbr-quick
89 comp: comp-vbr-quick
90
91 test-vbr-quick: proc-vbr-quick comp-vbr-quick
92 proc-vbr-quick: voice.src
93 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
94 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
95 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
96 comp-vbr-quick: voicevbr.arf
97 $(DIFF) voicvbra.tst voicevbr.arf
98 $(DIFF) voicvbrl.tst voicevbr.lrf
99 $(DIFF) voicvbru.tst voicevbr.urf
100
101 voice.src: tst-g726.zip
102 $(UNZIP) tst-g726.zip voice.src
103 sb -over voice.src
104
105 voicevbr.arf: tst-g726.zip
106 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
107 swapover voicevbr.arf voicevbr.lrf voicevbr.urf
108
109 # -----------------------------------------------------------------------------
110 # Test the implementation for g726demo (compliance)
111 # In the automatic compliance testing, g726demo.c is verified by test-tv
112 # For vbr-g726.c, no differences should be observed, since both use g726.c,
113 # and differ only on the demo logic. For full compliance testing of the
114 # vbr-g726.c program, use test-tv-vbr
115 # -----------------------------------------------------------------------------
116 test-tv: proc-tv-fix comp-tv
117 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
118 comp-tv-fix: comp-tv
119 comp-tv: comp16 comp24 comp32 comp40
120
121 proc16-fix:
122 #
123 # Process ADPCM/ Coder for normal and overload sequences, A law
124 #
125 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
126 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
127 #
128 # Process ADPCM/ Decoder for normal and overload sequences, A law
129 #
130 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
131 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
132 #
133 # Process ADPCM/ Cross-decoder for normal and overload sequences,
134 # A law input -> ADPCM 16kbit/s -> mu law output
135 #
136 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
137 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
138 #
139 #
140 # Process ADPCM/ Coder for normal and overload sequences, mu law
141 #
142 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
143 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
144 #
145 # Process ADPCM/ Decoder for normal and overload sequences, mu law
146 #
147 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
148 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
149 #
150 # Process ADPCM/ Cross-decoder for normal and overload sequences,
151 # mu law input -> ADPCM 16kbit/s -> A law output
152 #
153 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
154 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
155 #
156 #
157 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
158 #
159 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
160 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
161
162 comp16:
163 #
164 # =================================================================
165 # COMPARISON OF FILES !
166 # =================================================================
167 #
168 # Compare ADPCM/ Coder for normal and overload sequences, A law
169 #
170 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
171 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
172 #
173 # Compare ADPCM/ Decoder for normal and overload sequences, A law
174 #
175 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
176 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
177 #
178 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
179 # A law input -> ADPCM x kbit/s -> mu law output
180 #
181 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
182 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
183 #
184 #
185 # Compare ADPCM/ Coder for normal and overload sequences, mu law
186 #
187 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
188 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
189 #
190 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
191 #
192 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
193 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
194 #
195 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
196 # mu law input -> ADPCM x kbit/s -> A law output
197 #
198 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
199 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
200 #
201 #
202 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
203 #
204 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
205 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
206
207 proc24-fix:
208 #
209 #
210 # Process ADPCM/ Coder for normal and overload sequences, A law
211 #
212 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
213 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
214 #
215 # Process ADPCM/ Decoder for normal and overload sequences, A law
216 #
217 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
218 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
219 #
220 # Process ADPCM/ Cross-decoder for normal and overload sequences,
221 # A law input -> ADPCM 24kbit/s -> mu law output
222 #
223 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
224 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
225 #
226 #
227 # Process ADPCM/ Coder for normal and overload sequences, mu law
228 #
229 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
230 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
231 #
232 # Process ADPCM/ Decoder for normal and overload sequences, mu law
233 #
234 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
235 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
236 #
237 # Process ADPCM/ Cross-decoder for normal and overload sequences,
238 # mu law input -> ADPCM 24kbit/s -> A law output
239 #
240 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
241 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
242 #
243 #
244 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
245 #
246 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
247 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
248
249 comp24:
250 #
251 # =================================================================
252 # COMPARISON OF FILES !
253 # =================================================================
254 #
255 # Compare ADPCM/ Coder for normal and overload sequences, A law
256 #
257 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
258 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
259 #
260 # Compare ADPCM/ Decoder for normal and overload sequences, A law
261 #
262 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
263 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
264 #
265 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
266 # A law input -> ADPCM x kbit/s -> mu law output
267 #
268 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
269 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
270 #
271 #
272 # Compare ADPCM/ Coder for normal and overload sequences, mu law
273 #
274 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
275 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
276 #
277 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
278 #
279 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
280 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
281 #
282 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
283 # mu law input -> ADPCM x kbit/s -> A law output
284 #
285 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
286 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
287 #
288 #
289 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
290 #
291 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
292 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
293
294 proc32-fix:
295 #
296 # Process ADPCM/ Coder for normal and overload sequences, A law
297 #
298 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
299 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
300 #
301 # Process ADPCM/ Decoder for normal and overload sequences, A law
302 #
303 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
304 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
305 #
306 # Process ADPCM/ Cross-decoder for normal and overload sequences,
307 # A law input -> ADPCM 32kbit/s -> mu law output
308 #
309 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
310 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
311 #
312 #
313 # Process ADPCM/ Coder for normal and overload sequences, mu law
314 #
315 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
316 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
317 #
318 # Process ADPCM/ Decoder for normal and overload sequences, mu law
319 #
320 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
321 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
322 #
323 # Process ADPCM/ Cross-decoder for normal and overload sequences,
324 # mu law input -> ADPCM 32kbit/s -> A law output
325 #
326 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
327 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
328 #
329 #
330 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
331 #
332 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
333 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
334
335 comp32:
336 #
337 # =================================================================
338 # COMPARISON OF FILES !
339 # =================================================================
340 #
341 # Compare ADPCM/ Coder for normal and overload sequences, A law
342 #
343 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
344 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
345 #
346 # Compare ADPCM/ Decoder for normal and overload sequences, A law
347 #
348 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
349 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
350 #
351 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
352 # A law input -> ADPCM x kbit/s -> mu law output
353 #
354 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
355 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
356 #
357 #
358 # Compare ADPCM/ Coder for normal and overload sequences, mu law
359 #
360 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
361 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
362 #
363 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
364 #
365 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
366 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
367 #
368 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
369 # mu law input -> ADPCM x kbit/s -> A law output
370 #
371 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
372 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
373 #
374 #
375 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
376 #
377 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
378 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
379
380 proc40-fix:
381 #
382 #
383 # Process ADPCM/ Coder for normal and overload sequences, A law
384 #
385 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
386 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
387 #
388 # Process ADPCM/ Decoder for normal and overload sequences, A law
389 #
390 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
391 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
392 #
393 # Process ADPCM/ Cross-decoder for normal and overload sequences,
394 # A law input -> ADPCM 40kbit/s -> mu law output
395 #
396 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
397 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
398 #
399 #
400 # Process ADPCM/ Coder for normal and overload sequences, mu law
401 #
402 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
403 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
404 #
405 # Process ADPCM/ Decoder for normal and overload sequences, mu law
406 #
407 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
408 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
409 #
410 # Process ADPCM/ Cross-decoder for normal and overload sequences,
411 # mu law input -> ADPCM 40kbit/s -> A law output
412 #
413 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
414 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
415 #
416 #
417 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
418 #
419 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
420 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
421
422 comp40:
423 #
424 # =================================================================
425 # COMPARISON OF FILES !
426 # =================================================================
427 #
428 # Compare ADPCM/ Coder for normal and overload sequences, A law
429 #
430 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
431 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
432 #
433 # Compare ADPCM/ Decoder for normal and overload sequences, A law
434 #
435 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
436 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
437 #
438 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
439 # A law input -> ADPCM x kbit/s -> mu law output
440 #
441 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
442 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
443 #
444 #
445 # Compare ADPCM/ Coder for normal and overload sequences, mu law
446 #
447 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
448 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
449 #
450 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
451 #
452 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
453 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
454 #
455 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
456 # mu law input -> ADPCM x kbit/s -> A law output
457 #
458 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
459 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
460 #
461 #
462 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
463 #
464 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
465 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
466
467 #
468 # -----------------------------------------------------------------------------
469 # Test the implementation for vbr-g726 (compliance)
470 # -----------------------------------------------------------------------------
471 test-tv-vbr: proc-tv-vbr comp-tv
472 proc-tv-vbr: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
473 comp-vbr-tv: comp-tv
474
475 proc16-vbr:
476 # Process ADPCM/ Coder for normal and overload sequences, A law
477 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
478 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
479 # Process ADPCM/ Decoder for normal and overload sequences, A law
480 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
481 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
482 # Process ADPCM/ Cross-decoder for normal and overload sequences,
483 # A law input -> ADPCM 16kbit/s -> mu law output
484 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
485 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
486 # Process ADPCM/ Coder for normal and overload sequences, mu law
487 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
488 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
489 # Process ADPCM/ Decoder for normal and overload sequences, mu law
490 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
491 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
492 # Process ADPCM/ Cross-decoder for normal and overload sequences,
493 # mu law input -> ADPCM 16kbit/s ->A law output
494 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
495 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
496 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
497 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
498 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
499
500 proc24-vbr:
501 # Process ADPCM/ Coder for normal and overload sequences, A law
502 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
503 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
504 # Process ADPCM/ Decoder for normal and overload sequences, A law
505 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
506 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
507 # Process ADPCM/ Cross-decoder for normal and overload sequences,
508 # A law input -> ADPCM 24kbit/s -> mu law output
509 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
510 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
511 # Process ADPCM/ Coder for normal and overload sequences, mu law
512 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
513 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
514 # Process ADPCM/ Decoder for normal and overload sequences, mu law
515 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
516 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
517 # Process ADPCM/ Cross-decoder for normal and overload sequences,
518 # mu law input -> ADPCM 24kbit/s ->A law output
519 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
520 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
521 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
522 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
523 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
524
525 proc32-vbr:
526 # Process ADPCM/ Coder for normal and overload sequences, A law
527 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
528 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
529 # Process ADPCM/ Decoder for normal and overload sequences, A law
530 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
531 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
532 # Process ADPCM/ Cross-decoder for normal and overload sequences,
533 # A law input -> ADPCM 32kbit/s -> mu law output
534 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
535 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
536 # Process ADPCM/ Coder for normal and overload sequences, mu law
537 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
538 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
539 # Process ADPCM/ Decoder for normal and overload sequences, mu law
540 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
541 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
542 # Process ADPCM/ Cross-decoder for normal and overload sequences,
543 # mu law input -> ADPCM 32kbit/s ->A law output
544 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
545 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
546 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
547 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
548 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
549
550 proc40-vbr:
551 # Process ADPCM/ Coder for normal and overload sequences, A law
552 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
553 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
554 # Process ADPCM/ Decoder for normal and overload sequences, A law
555 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
556 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
557 # Process ADPCM/ Cross-decoder for normal and overload sequences,
558 # A law input -> ADPCM 40kbit/s -> mu law output
559 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
560 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
561 # Process ADPCM/ Coder for normal and overload sequences, mu law
562 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
563 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
564 # Process ADPCM/ Decoder for normal and overload sequences, mu law
565 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
566 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
567 # Process ADPCM/ Cross-decoder for normal and overload sequences,
568 # mu law input -> ADPCM 40kbit/s ->A law output
569 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
570 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
571 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
572 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
573 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
574
575
576

Repositories maintained by Peter Meerwald, pmeerw@pmeerw.net.