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comparison intercom/g726/makefile.unx @ 2:13be24d74cd2

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import intercom-0.4.1
author Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date Fri, 25 Jun 2010 09:57:52 +0200
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1:9cadc470e3da 2:13be24d74cd2
1 # -----------------------------------------------------------------------------
2 # Unix makefile for compiling and testing the G.726 implementation
3 # The executable must be defined by variable G726 below.
4 # 01.May.94 - Implemented by <simao@cpqd.ansp.br>
5 # 10.Mar.95 - Compilation and test sequence processing/comparison for
6 # vbr-g726.c. <simao@ctd.comsat.com>
7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
8 # order to perform the (optional) compliance test.
9 # -----------------------------------------------------------------------------
10
11 # ------------------------------------------------
12 # Choose compiler. Sun: use cc. HP: gotta use gcc
13 # ------------------------------------------------
14 CC=gcc
15 CC_OPT = -Wall -g -I../utl
16
17 # ------------------------------------------------
18 # General purpose symbols
19 # ------------------------------------------------
20 G726 = ./g726demo
21 VBR = ./vbr-g726 -q
22 # DIFF = cf -q
23 DIFF = diff
24
25 # ------------------------------------------------
26 # Choose an archiving utility:
27 # - public domain unzip, or [PC/Unix/VMS]
28 # - shareware pkunzip [PC only]
29 # ------------------------------------------------
30 #UNZIP = pkunzip
31 UNZIP = unzip -o
32
33 # ------------------------------------------------
34 # File lists
35 # ------------------------------------------------
36 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
37
38 DEMO_OBJ = g726demo.o g726.o
39 VBR_OBJ = vbr-g726.o g726.o g711.o
40
41 # ------------------------------------------------
42 # Targets
43 # ------------------------------------------------
44 all:: g726demo vbr-g726
45
46 anyway: clean all
47
48 clean:
49 $(RM) *.o
50
51 cleantest:
52 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
53 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
54
55 veryclean: clean cleantest
56 $(RM) g726demo vbr-g726
57
58 # -----------------------------------------------------------------------------
59 # Generic rules
60 # -----------------------------------------------------------------------------
61 .c.o:
62 $(CC) $(CC_OPT) -c $<
63
64 # -----------------------------------------------------------------------------
65 # Specific rules
66 # -----------------------------------------------------------------------------
67 vbr-g726: $(VBR_OBJ)
68 $(CC) -o vbr-g726 $(VBR_OBJ) -lm
69
70 g726demo: $(DEMO_OBJ)
71 $(CC) -o g726demo $(DEMO_OBJ) -lm
72
73 g726demo.o: g726demo.c
74 $(CC) -c $(CC_OPT) -I../g711 g726demo.c
75
76 g726.o: g726.c
77 $(CC) -c $(CC_OPT) g726.c
78
79 g711.o: ../g711/g711.c
80 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
81
82 vbr-g726.o: vbr-g726.c
83 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
84
85 # ----------------------------------------
86 # Very simple portability test
87 # ----------------------------------------
88 test: test-vbr-quick
89 proc: proc-vbr-quick
90 comp: comp-vbr-quick
91
92 test-vbr-quick: proc-vbr-quick comp-vbr-quick
93 proc-vbr-quick: voice.src
94 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
95 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
96 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
97 comp-vbr-quick: voicevbr.arf
98 $(DIFF) voicvbra.tst voicevbr.arf
99 $(DIFF) voicvbrl.tst voicevbr.lrf
100 $(DIFF) voicvbru.tst voicevbr.urf
101
102 voice.src: tst-g726.zip
103 $(UNZIP) tst-g726.zip voice.src
104 sb -over -if little voice.src
105
106 voicevbr.arf: tst-g726.zip
107 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
108 swapover -if little voicevbr.arf voicevbr.lrf voicevbr.urf
109
110 # -----------------------------------------------------------------------------
111 # Test the implementation for g726demo (compliance)
112 # In the automatic compliance testing, g726demo.c is verified by test-tv
113 # For vbr-g726.c, no differences should be observed, since both use g726.c,
114 # and differ only on the demo logic. For full compliance testing of the
115 # vbr-g726.c program, use test-tv-vbr
116 # -----------------------------------------------------------------------------
117 test-tv: proc-tv-fix comp-tv
118 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
119 comp-tv-fix: comp-tv
120 comp-tv: comp16 comp24 comp32 comp40
121
122 proc16-fix:
123 #
124 # Process ADPCM/ Coder for normal and overload sequences, A law
125 #
126 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
127 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
128 #
129 # Process ADPCM/ Decoder for normal and overload sequences, A law
130 #
131 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
132 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
133 #
134 # Process ADPCM/ Cross-decoder for normal and overload sequences,
135 # A law input -> ADPCM 16kbit/s -> mu law output
136 #
137 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
138 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
139 #
140 #
141 # Process ADPCM/ Coder for normal and overload sequences, mu law
142 #
143 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
144 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
145 #
146 # Process ADPCM/ Decoder for normal and overload sequences, mu law
147 #
148 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
149 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
150 #
151 # Process ADPCM/ Cross-decoder for normal and overload sequences,
152 # mu law input -> ADPCM 16kbit/s -> A law output
153 #
154 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
155 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
156 #
157 #
158 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
159 #
160 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
161 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
162
163 comp16:
164 #
165 # =================================================================
166 # COMPARISON OF FILES !
167 # =================================================================
168 #
169 # Compare ADPCM/ Coder for normal and overload sequences, A law
170 #
171 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
172 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
173 #
174 # Compare ADPCM/ Decoder for normal and overload sequences, A law
175 #
176 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
177 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
178 #
179 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
180 # A law input -> ADPCM x kbit/s -> mu law output
181 #
182 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
183 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
184 #
185 #
186 # Compare ADPCM/ Coder for normal and overload sequences, mu law
187 #
188 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
189 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
190 #
191 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
192 #
193 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
194 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
195 #
196 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
197 # mu law input -> ADPCM x kbit/s -> A law output
198 #
199 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
200 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
201 #
202 #
203 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
204 #
205 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
206 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
207
208 proc24-fix:
209 #
210 #
211 # Process ADPCM/ Coder for normal and overload sequences, A law
212 #
213 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
214 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
215 #
216 # Process ADPCM/ Decoder for normal and overload sequences, A law
217 #
218 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
219 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
220 #
221 # Process ADPCM/ Cross-decoder for normal and overload sequences,
222 # A law input -> ADPCM 24kbit/s -> mu law output
223 #
224 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
225 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
226 #
227 #
228 # Process ADPCM/ Coder for normal and overload sequences, mu law
229 #
230 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
231 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
232 #
233 # Process ADPCM/ Decoder for normal and overload sequences, mu law
234 #
235 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
236 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
237 #
238 # Process ADPCM/ Cross-decoder for normal and overload sequences,
239 # mu law input -> ADPCM 24kbit/s -> A law output
240 #
241 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
242 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
243 #
244 #
245 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
246 #
247 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
248 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
249
250 comp24:
251 #
252 # =================================================================
253 # COMPARISON OF FILES !
254 # =================================================================
255 #
256 # Compare ADPCM/ Coder for normal and overload sequences, A law
257 #
258 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
259 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
260 #
261 # Compare ADPCM/ Decoder for normal and overload sequences, A law
262 #
263 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
264 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
265 #
266 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
267 # A law input -> ADPCM x kbit/s -> mu law output
268 #
269 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
270 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
271 #
272 #
273 # Compare ADPCM/ Coder for normal and overload sequences, mu law
274 #
275 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
276 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
277 #
278 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
279 #
280 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
281 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
282 #
283 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
284 # mu law input -> ADPCM x kbit/s -> A law output
285 #
286 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
287 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
288 #
289 #
290 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
291 #
292 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
293 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
294
295 proc32-fix:
296 #
297 # Process ADPCM/ Coder for normal and overload sequences, A law
298 #
299 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
300 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
301 #
302 # Process ADPCM/ Decoder for normal and overload sequences, A law
303 #
304 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
305 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
306 #
307 # Process ADPCM/ Cross-decoder for normal and overload sequences,
308 # A law input -> ADPCM 32kbit/s -> mu law output
309 #
310 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
311 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
312 #
313 #
314 # Process ADPCM/ Coder for normal and overload sequences, mu law
315 #
316 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
317 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
318 #
319 # Process ADPCM/ Decoder for normal and overload sequences, mu law
320 #
321 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
322 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
323 #
324 # Process ADPCM/ Cross-decoder for normal and overload sequences,
325 # mu law input -> ADPCM 32kbit/s -> A law output
326 #
327 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
328 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
329 #
330 #
331 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
332 #
333 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
334 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
335
336 comp32:
337 #
338 # =================================================================
339 # COMPARISON OF FILES !
340 # =================================================================
341 #
342 # Compare ADPCM/ Coder for normal and overload sequences, A law
343 #
344 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
345 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
346 #
347 # Compare ADPCM/ Decoder for normal and overload sequences, A law
348 #
349 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
350 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
351 #
352 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
353 # A law input -> ADPCM x kbit/s -> mu law output
354 #
355 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
356 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
357 #
358 #
359 # Compare ADPCM/ Coder for normal and overload sequences, mu law
360 #
361 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
362 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
363 #
364 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
365 #
366 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
367 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
368 #
369 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
370 # mu law input -> ADPCM x kbit/s -> A law output
371 #
372 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
373 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
374 #
375 #
376 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
377 #
378 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
379 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
380
381 proc40-fix:
382 #
383 #
384 # Process ADPCM/ Coder for normal and overload sequences, A law
385 #
386 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
387 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
388 #
389 # Process ADPCM/ Decoder for normal and overload sequences, A law
390 #
391 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
392 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
393 #
394 # Process ADPCM/ Cross-decoder for normal and overload sequences,
395 # A law input -> ADPCM 40kbit/s -> mu law output
396 #
397 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
398 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
399 #
400 #
401 # Process ADPCM/ Coder for normal and overload sequences, mu law
402 #
403 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
404 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
405 #
406 # Process ADPCM/ Decoder for normal and overload sequences, mu law
407 #
408 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
409 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
410 #
411 # Process ADPCM/ Cross-decoder for normal and overload sequences,
412 # mu law input -> ADPCM 40kbit/s -> A law output
413 #
414 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
415 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
416 #
417 #
418 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
419 #
420 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
421 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
422
423 comp40:
424 #
425 # =================================================================
426 # COMPARISON OF FILES !
427 # =================================================================
428 #
429 # Compare ADPCM/ Coder for normal and overload sequences, A law
430 #
431 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
432 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
433 #
434 # Compare ADPCM/ Decoder for normal and overload sequences, A law
435 #
436 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
437 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
438 #
439 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
440 # A law input -> ADPCM x kbit/s -> mu law output
441 #
442 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
443 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
444 #
445 #
446 # Compare ADPCM/ Coder for normal and overload sequences, mu law
447 #
448 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
449 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
450 #
451 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
452 #
453 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
454 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
455 #
456 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
457 # mu law input -> ADPCM x kbit/s -> A law output
458 #
459 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
460 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
461 #
462 #
463 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
464 #
465 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
466 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
467
468 #
469 # ----------------------------------------------------------------------------
470 # Test the implementation for vbr-g726 (compliance)
471 # ----------------------------------------------------------------------------
472 test-vbr: proc-vbr comp-tv
473 proc-vbr: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
474 comp-vbr-tv: comp-tv
475
476 proc16-vbr:
477 # Process ADPCM/ Coder for normal and overload sequences, A law
478 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
479 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
480 # Process ADPCM/ Decoder for normal and overload sequences, A law
481 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
482 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
483 # Process ADPCM/ Cross-decoder for normal and overload sequences,
484 # A law input -> ADPCM 16kbit/s -> mu law output
485 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
486 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
487 # Process ADPCM/ Coder for normal and overload sequences, mu law
488 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
489 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
490 # Process ADPCM/ Decoder for normal and overload sequences, mu law
491 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
492 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
493 # Process ADPCM/ Cross-decoder for normal and overload sequences,
494 # mu law input -> ADPCM 16kbit/s ->A law output
495 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
496 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
497 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
498 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
499 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
500
501 proc24-vbr:
502 # Process ADPCM/ Coder for normal and overload sequences, A law
503 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
504 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
505 # Process ADPCM/ Decoder for normal and overload sequences, A law
506 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
507 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
508 # Process ADPCM/ Cross-decoder for normal and overload sequences,
509 # A law input -> ADPCM 24kbit/s -> mu law output
510 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
511 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
512 # Process ADPCM/ Coder for normal and overload sequences, mu law
513 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
514 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
515 # Process ADPCM/ Decoder for normal and overload sequences, mu law
516 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
517 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
518 # Process ADPCM/ Cross-decoder for normal and overload sequences,
519 # mu law input -> ADPCM 24kbit/s ->A law output
520 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
521 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
522 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
523 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
524 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
525
526 proc32-vbr:
527 # Process ADPCM/ Coder for normal and overload sequences, A law
528 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
529 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
530 # Process ADPCM/ Decoder for normal and overload sequences, A law
531 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
532 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
533 # Process ADPCM/ Cross-decoder for normal and overload sequences,
534 # A law input -> ADPCM 32kbit/s -> mu law output
535 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
536 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
537 # Process ADPCM/ Coder for normal and overload sequences, mu law
538 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
539 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
540 # Process ADPCM/ Decoder for normal and overload sequences, mu law
541 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
542 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
543 # Process ADPCM/ Cross-decoder for normal and overload sequences,
544 # mu law input -> ADPCM 32kbit/s ->A law output
545 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
546 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
547 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
548 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
549 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
550
551 proc40-vbr:
552 # Process ADPCM/ Coder for normal and overload sequences, A law
553 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
554 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
555 # Process ADPCM/ Decoder for normal and overload sequences, A law
556 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
557 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
558 # Process ADPCM/ Cross-decoder for normal and overload sequences,
559 # A law input -> ADPCM 40kbit/s -> mu law output
560 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
561 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
562 # Process ADPCM/ Coder for normal and overload sequences, mu law
563 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
564 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
565 # Process ADPCM/ Decoder for normal and overload sequences, mu law
566 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
567 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
568 # Process ADPCM/ Cross-decoder for normal and overload sequences,
569 # mu law input -> ADPCM 40kbit/s ->A law output
570 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
571 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
572 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
573 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
574 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
575
576 # =========================================
577 # Process by batch
578 # =========================================
579 batchtest:
580 batch test-g726
581
582 batchtest-vbr:
583 echo make -f makefile.unx test-vbr | batch

Repositories maintained by Peter Meerwald, pmeerw@pmeerw.net.