--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/spandsp-0.0.3/spandsp-0.0.3/src/msvc/spandsp.def	Fri Jun 25 16:00:21 2010 +0200
@@ -0,0 +1,304 @@
+EXPORTS
+adsi_rx_init
+adsi_rx
+adsi_tx_init
+adsi_send_alert_tone
+adsi_put_message
+adsi_next_field
+adsi_add_field
+async_tx_init
+async_rx_init
+awgn
+bert_init
+bert_get_bit
+bert_put_bit
+bert_set_report
+bert_result
+filter_create
+filter_delete
+filter_step
+cfilter_create
+cfilter_delete
+cfilter_step
+dds_phase_rate
+dds_frequency
+dds_scaling_dbm0
+dds_scaling_dbov
+dds_lookup
+dds_offset
+dds
+dds_mod
+dds_complex
+dds_complex_mod
+dds_phase_ratef
+dds_frequencyf
+dds_scaling_dbm0f
+dds_scaling_dbovf
+ddsf
+dds_modf
+dds_complexf
+dds_complex_modf
+echo_can_create
+echo_can_free
+echo_can_flush
+echo_can_adaption_mode
+echo_can_update
+fax_rx
+fax_tx
+fax_set_flush_handler
+fax_init
+fax_release
+fsk_tx_init
+fsk_tx_power
+fsk_tx_set_get_bit
+fsk_tx
+fsk_rx_signal_power
+fsk_rx_signal_cutoff
+fsk_rx_init
+fsk_rx
+fsk_rx_set_put_bit
+g722_encode_init
+g722_encode_release
+g722_encode
+g722_decode_init
+g722_decode_release
+g722_decode
+g726_init
+g726_release
+crc_itu32_calc
+crc_itu32_append
+crc_itu32_check
+crc_itu16_calc
+crc_itu16_append
+crc_itu16_check
+hdlc_rx_init
+hdlc_rx_get_stats
+hdlc_tx_init
+hdlc_tx_frame
+hdlc_tx_preamble
+ima_adpcm_init
+ima_adpcm_release
+span_log_test
+span_log
+span_log_buf
+span_log_init
+span_log_set_protocol
+span_set_message_handler
+span_set_error_handler
+modem_echo_can_create
+modem_echo_can_free
+modem_echo_can_flush
+modem_echo_can_adaption_mode
+modem_echo_can_update
+noise
+oki_adpcm_init
+oki_adpcm_release
+playout_put
+playout_get
+playout_get_unconditional
+playout_current_length
+playout_next_due
+playout_new
+playout_free
+playout_restart
+plc_rx
+plc_fillin
+plc_init
+plc_release
+power_meter_init
+power_meter_damping
+power_meter_update
+power_meter_dbm0
+power_meter_dbov
+power_meter_level_dbm0
+power_meter_level_dbov
+queue_empty
+queue_free_space
+queue_contents
+queue_flush
+queue_view
+queue_read
+queue_write
+queue_test_msg
+queue_read_msg
+queue_write_msg
+queue_create
+queue_delete
+sig_tone_init
+sig_tone_rx
+sig_tone_tx
+super_tone_rx_make_descriptor
+super_tone_rx_add_tone
+super_tone_rx_add_element
+super_tone_rx_init
+super_tone_rx_free
+super_tone_rx_segment_callback
+super_tone_rx
+super_tone_tx_make_step
+super_tone_tx_free
+super_tone_tx_init
+super_tone_tx
+t30_init
+t30_release
+t30_restart
+t30_create
+t30_free
+t30_frametype
+t30_decode_dis_dtc_dcs
+t30_completion_code_to_str
+t30_set_header_info
+t30_set_local_ident
+t30_get_sub_address
+t30_get_header_info
+t30_get_local_ident
+t30_get_far_ident
+t30_get_transfer_statistics
+t30_set_phase_b_handler
+t30_set_phase_d_handler
+t30_set_phase_e_handler
+t30_set_document_handler
+t30_set_rx_file
+t30_set_tx_file
+t30_local_interrupt_request
+t30_send_complete
+t30_hdlc_accept
+t30_timer_update
+t31_call_event
+t31_at_rx
+t31_rx
+t31_tx
+t31_init
+t31_release
+t35_decode
+t38_indicator
+t38_data_type
+t38_field_type
+t38_terminal_init
+t38_gateway_init
+t4_rx_create
+t4_rx_init
+t4_rx_start_page
+t4_rx_end_page
+t4_rx_delete
+t4_rx_end
+t4_rx_set_rx_encoding
+t4_rx_set_sub_address
+t4_rx_set_far_ident
+t4_rx_set_vendor
+t4_rx_set_model
+t4_tx_create
+t4_tx_init
+t4_tx_start_page
+t4_tx_restart_page
+t4_tx_end_page
+t4_tx_delete
+t4_tx_end
+t4_tx_set_tx_encoding
+t4_tx_set_min_row_bits
+t4_tx_set_local_ident
+t4_tx_set_header_info
+t4_get_transfer_statistics
+t4_encoding_to_str
+time_scale_init
+time_scale_rate
+time_scale
+make_goertzel_descriptor
+goertzel_init
+goertzel_update
+goertzel_result
+dtmf_rx_init
+dtmf_rx_set_realtime_callback
+dtmf_rx_parms
+dtmf_rx
+make_tone_descriptor
+make_tone_gen_descriptor
+tone_gen_init
+tone_gen
+dtmf_tx_init
+dtmf_tx
+v17_rx_init
+v17_rx_restart
+v17_rx_release
+v17_rx_set_put_bit
+v17_rx
+v17_rx_equalizer_state
+v17_rx_carrier_frequency
+v17_rx_symbol_timing_correction
+v17_rx_signal_power
+v17_rx_signal_cutoff
+v17_rx_set_qam_report_handler
+v17_tx_power
+v17_tx_init
+v17_tx_restart
+v17_tx_release
+v17_tx_set_get_bit
+v17_tx
+v22bis_rx_restart
+v22bis_rx
+v22bis_rx_equalizer_state
+v22bis_rx_carrier_frequency
+v22bis_rx_symbol_timing_correction
+v22bis_rx_signal_power
+v22bis_rx_set_qam_report_handler
+v22bis_tx
+v22bis_tx_power
+v22bis_restart
+v22bis_init
+v22bis_set_get_bit
+v22bis_set_put_bit
+v27ter_rx_init
+v27ter_rx_restart
+v27ter_rx_release
+v27ter_rx_set_put_bit
+v27ter_rx
+v27ter_rx_equalizer_state
+v27ter_rx_carrier_frequency
+v27ter_rx_symbol_timing_correction
+v27ter_rx_signal_power
+v27ter_rx_signal_cutoff
+v27ter_rx_set_qam_report_handler
+v27ter_tx_power
+v27ter_tx_init
+v27ter_tx_restart
+v27ter_tx_release
+v27ter_tx_set_get_bit
+v27ter_tx
+v29_rx_init
+v29_rx_restart
+v29_rx_release
+v29_rx_set_put_bit
+v29_rx
+v29_rx_equalizer_state
+v29_rx_carrier_frequency
+v29_rx_symbol_timing_correction
+v29_rx_signal_power
+v29_rx_signal_cutoff
+v29_rx_set_qam_report_handler
+v29_tx_power
+v29_tx_init
+v29_tx_restart
+v29_tx_release
+v29_tx_set_get_bit
+v29_tx
+lapm_dump
+lapm_receive
+lapm_tx
+lapm_tx_iframe
+v42_set_status_callback
+v42_rx_bit
+v42_tx_bit
+v42_init
+v42_restart
+v42_release
+v42bis_compress
+v42bis_compress_flush
+v42bis_decompress
+v42bis_decompress_flush
+v42bis_init
+v42bis_release
+v8_init
+v8_release
+v8_tx
+v8_rx
+v8_log_supported_modulations
+