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annotate spandsp-0.0.6pre17/config/ax_misaligned_access_fails.m4 @ 4:26cd8f1ef0b1

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import spandsp-0.0.6pre17
author Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date Fri, 25 Jun 2010 15:50:58 +0200
parents
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1 # AX_MISALIGNED_ACCESS_FAILS(MACHINE, [ACTION-IF-MISALIGNED-FAILS], [ACTION-IF-MISALIGNED-OK])
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
2 # -------------------------------------------------------------------------------------
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
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3 #
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
4 # Check if a specified machine type cannot handle misaligned data. That is, multi-byte data
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
5 # types which are not properly aligned in memory fail. Many machines are happy to work with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
6 # misaligned data, but slowing down a bit. Other machines just won't tolerate such data.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
7 #
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
8 # This is a simple lookup amongst machines known to the current autotools. So far we only deal
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
9 # with the ARM and sparc.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
10 # A lookup is used, as many of the devices which cannot handled misaligned access are embedded
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
11 # processors, for which the code normally be cross-compiled.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
12 #
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
13 AC_DEFUN([AX_MISALIGNED_ACCESS_FAILS],
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
14 [AS_VAR_PUSHDEF([ac_MisalignedAccessFails], [ac_cv_misaligned_access_fails_$1])dnl
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
15 AC_CACHE_CHECK([if $1 fails on misaligned memory access], ac_MisalignedAccessFails,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
16 [case $1 in
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
17 arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] \
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
18 | bfin \
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
19 | sparc \
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
20 | xscale | xscalee[bl] \
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
21 | arm-* | armbe-* | armle-* | armeb-* | armv*-* \
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
22 | bfin-* \
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
23 | sparc-* \
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
24 | xscale-* | xscalee[bl]-* )
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
25 AS_VAR_SET(ac_MisalignedAccessFails, yes)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
26 ;;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
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27 *)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
28 AS_VAR_SET(ac_MisalignedAccessFails, no)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
29 ;;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
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30 esac])
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
31 AS_IF([test AS_VAR_GET(ac_MisalignedAccessFails) = yes], [$2], [$3])[]dnl
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
32 AS_VAR_POPDEF([ac_MisalignedAccessFails])dnl
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
33 ])# MISALIGNED_ACCESS_FAILS

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