Mercurial > hg > audiostuff

annotate spandsp-0.0.6pre17/src/t38_terminal.c @ 4:26cd8f1ef0b1

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
import spandsp-0.0.6pre17
author Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date Fri, 25 Jun 2010 15:50:58 +0200
parents
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
4
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1 /*
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
2 * SpanDSP - a series of DSP components for telephony
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
3 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
4 * t38_terminal.c - T.38 termination, less the packet exchange part
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
5 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
6 * Written by Steve Underwood <steveu@coppice.org>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
7 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
8 * Copyright (C) 2005, 2006, 2008 Steve Underwood
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
9 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
10 * All rights reserved.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
11 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
12 * This program is free software; you can redistribute it and/or modify
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
13 * it under the terms of the GNU Lesser General Public License version 2.1,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
14 * as published by the Free Software Foundation.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
15 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
16 * This program is distributed in the hope that it will be useful,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
19 * GNU Lesser General Public License for more details.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
20 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
21 * You should have received a copy of the GNU Lesser General Public
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
22 * License along with this program; if not, write to the Free Software
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
24 *
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
25 * $Id: t38_terminal.c,v 1.129.4.2 2009/12/19 10:44:10 steveu Exp $
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
26 */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
27
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
28 /*! \file */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
29
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
30 #if defined(HAVE_CONFIG_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
31 #include "config.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
32 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
33
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
34 #include <inttypes.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
35 #include <stdlib.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
36 #include <stdio.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
37 #include <fcntl.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
38 #include <time.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
39 #include <string.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
40 #if defined(HAVE_TGMATH_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
41 #include <tgmath.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
42 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
43 #if defined(HAVE_MATH_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
44 #include <math.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
45 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
46 #include "floating_fudge.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
47 #include <assert.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
48 #include <tiffio.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
49
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
50 #include "spandsp/telephony.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
51 #include "spandsp/logging.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
52 #include "spandsp/bit_operations.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
53 #include "spandsp/queue.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
54 #include "spandsp/power_meter.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
55 #include "spandsp/complex.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
56 #include "spandsp/tone_generate.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
57 #include "spandsp/async.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
58 #include "spandsp/hdlc.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
59 #include "spandsp/fsk.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
60 #include "spandsp/v29tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
61 #include "spandsp/v29rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
62 #include "spandsp/v27ter_tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
63 #include "spandsp/v27ter_rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
64 #include "spandsp/v17tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
65 #include "spandsp/v17rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
66 #include "spandsp/t4_rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
67 #include "spandsp/t4_tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
68 #include "spandsp/t30_fcf.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
69 #include "spandsp/t35.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
70 #include "spandsp/t30.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
71 #include "spandsp/t30_api.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
72 #include "spandsp/t30_logging.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
73 #include "spandsp/t38_core.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
74 #include "spandsp/t38_terminal.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
75
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
76 #include "spandsp/private/logging.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
77 #include "spandsp/private/t4_rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
78 #include "spandsp/private/t4_tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
79 #include "spandsp/private/t30.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
80 #include "spandsp/private/t38_core.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
81 #include "spandsp/private/t38_terminal.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
82
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
83 /* Settings suitable for paced transmission over a UDP transport */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
84 #define MS_PER_TX_CHUNK 30
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
85
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
86 #define INDICATOR_TX_COUNT 3
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
87 #define DATA_TX_COUNT 1
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
88 #define DATA_END_TX_COUNT 3
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
89
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
90 /* Settings suitable for unpaced transmission over a TCP transport */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
91 #define MAX_OCTETS_PER_UNPACED_CHUNK 300
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
92
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
93 /* Backstop timeout if reception of packets stops in the middle of a burst */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
94 #define MID_RX_TIMEOUT 15000
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
95
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
96 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
97 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
98 T38_CHUNKING_MERGE_FCS_WITH_DATA = 0x0001,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
99 T38_CHUNKING_WHOLE_FRAMES = 0x0002,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
100 T38_CHUNKING_ALLOW_TEP_TIME = 0x0004
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
101 };
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
102
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
103 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
104 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
105 T38_TIMED_STEP_NONE = 0,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
106 T38_TIMED_STEP_NON_ECM_MODEM = 0x10,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
107 T38_TIMED_STEP_NON_ECM_MODEM_2 = 0x11,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
108 T38_TIMED_STEP_NON_ECM_MODEM_3 = 0x12,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
109 T38_TIMED_STEP_NON_ECM_MODEM_4 = 0x13,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
110 T38_TIMED_STEP_NON_ECM_MODEM_5 = 0x14,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
111 T38_TIMED_STEP_HDLC_MODEM = 0x20,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
112 T38_TIMED_STEP_HDLC_MODEM_2 = 0x21,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
113 T38_TIMED_STEP_HDLC_MODEM_3 = 0x22,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
114 T38_TIMED_STEP_HDLC_MODEM_4 = 0x23,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
115 T38_TIMED_STEP_HDLC_MODEM_5 = 0x24,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
116 T38_TIMED_STEP_CED = 0x30,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
117 T38_TIMED_STEP_CED_2 = 0x31,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
118 T38_TIMED_STEP_CED_3 = 0x32,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
119 T38_TIMED_STEP_CNG = 0x40,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
120 T38_TIMED_STEP_CNG_2 = 0x41,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
121 T38_TIMED_STEP_PAUSE = 0x50
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
122 };
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
123
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
124 static __inline__ void front_end_status(t38_terminal_state_t *s, int status)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
125 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
126 t30_front_end_status(&s->t30, status);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
127 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
128 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
129
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
130 static __inline__ void hdlc_accept_frame(t38_terminal_state_t *s, const uint8_t *msg, int len, int ok)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
131 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
132 t30_hdlc_accept(&s->t30, msg, len, ok);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
133 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
134 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
135
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
136 static int extra_bits_in_stuffed_frame(const uint8_t buf[], int len)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
137 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
138 int bitstream;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
139 int ones;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
140 int stuffed;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
141 int i;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
142 int j;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
143
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
144 bitstream = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
145 ones = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
146 stuffed = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
147 /* We should really append the CRC, and include the stuffed bits for that, to get
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
148 the exact number of bits in the frame. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
149 //len = crc_itu16_append(buf, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
150 for (i = 0; i < len; i++)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
151 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
152 bitstream = buf[i];
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
153 for (j = 0; j < 8; j++)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
154 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
155 if ((bitstream & 1))
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
156 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
157 if (++ones >= 5)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
158 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
159 ones = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
160 stuffed++;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
161 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
162 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
163 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
164 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
165 ones = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
166 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
167 bitstream >>= 1;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
168 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
169 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
170 /* The total length of the frame is:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
171 the number of bits in the body
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
172 + the number of additional bits in the body due to stuffing
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
173 + the number of bits in the CRC
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
174 + the number of additional bits in the CRC due to stuffing
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
175 + 16 bits for the two terminating flag octets.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
176 Lets just allow 3 bits for the CRC, which is the worst case. It
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
177 avoids calculating the real CRC, and the worst it can do is cause
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
178 a flag octet's worth of additional output.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
179 */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
180 return stuffed + 16 + 3 + 16;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
181 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
182 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
183
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
184 static int process_rx_missing(t38_core_state_t *t, void *user_data, int rx_seq_no, int expected_seq_no)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
185 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
186 t38_terminal_state_t *s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
187
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
188 s = (t38_terminal_state_t *) user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
189 s->t38_fe.rx_data_missing = TRUE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
190 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
191 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
192 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
193
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
194 static int process_rx_indicator(t38_core_state_t *t, void *user_data, int indicator)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
195 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
196 t38_terminal_state_t *s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
197 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
198
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
199 s = (t38_terminal_state_t *) user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
200 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
201
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
202 if (t->current_rx_indicator == indicator)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
203 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
204 /* This is probably due to the far end repeating itself, or slipping
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
205 preamble messages in between HDLC frames. T.38/V.1.3 tells us to
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
206 ignore it. Its harmless. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
207 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
208 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
209 /* In termination mode we don't care very much about indicators telling us training
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
210 is starting. We only care about V.21 preamble starting, for timeout control, and
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
211 the actual data. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
212 switch (indicator)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
213 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
214 case T38_IND_NO_SIGNAL:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
215 if (t->current_rx_indicator == T38_IND_V21_PREAMBLE
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
216 &&
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
217 (fe->current_rx_type == T30_MODEM_V21 || fe->current_rx_type == T30_MODEM_CNG))
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
218 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
219 hdlc_accept_frame(s, NULL, SIG_STATUS_CARRIER_DOWN, TRUE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
220 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
221 fe->timeout_rx_samples = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
222 front_end_status(s, T30_FRONT_END_SIGNAL_ABSENT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
223 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
224 case T38_IND_CNG:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
225 /* We are completely indifferent to the startup tones. They serve no purpose for us.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
226 We can't even assume that the existance of a tone means the far end is achieving
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
227 proper communication. Some T.38 gateways will just send out a CED or CNG indicator
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
228 without having seen anything from the far end FAX terminal.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
229 Just report them for completeness. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
230 front_end_status(s, T30_FRONT_END_CNG_PRESENT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
231 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
232 case T38_IND_CED:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
233 front_end_status(s, T30_FRONT_END_CED_PRESENT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
234 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
235 case T38_IND_V21_PREAMBLE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
236 fe->timeout_rx_samples = fe->samples + ms_to_samples(MID_RX_TIMEOUT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
237 front_end_status(s, T30_FRONT_END_SIGNAL_PRESENT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
238 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
239 case T38_IND_V27TER_2400_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
240 case T38_IND_V27TER_4800_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
241 case T38_IND_V29_7200_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
242 case T38_IND_V29_9600_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
243 case T38_IND_V17_7200_SHORT_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
244 case T38_IND_V17_7200_LONG_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
245 case T38_IND_V17_9600_SHORT_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
246 case T38_IND_V17_9600_LONG_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
247 case T38_IND_V17_12000_SHORT_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
248 case T38_IND_V17_12000_LONG_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
249 case T38_IND_V17_14400_SHORT_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
250 case T38_IND_V17_14400_LONG_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
251 case T38_IND_V34_CNTL_CHANNEL_1200:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
252 case T38_IND_V34_PRI_CHANNEL:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
253 case T38_IND_V33_12000_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
254 case T38_IND_V33_14400_TRAINING:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
255 /* We really don't care what kind of modem is delivering the following image data.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
256 We only care that some kind of fast modem signal is coming next. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
257 fe->timeout_rx_samples = fe->samples + ms_to_samples(MID_RX_TIMEOUT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
258 front_end_status(s, T30_FRONT_END_SIGNAL_PRESENT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
259 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
260 case T38_IND_V8_ANSAM:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
261 case T38_IND_V8_SIGNAL:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
262 case T38_IND_V34_CC_RETRAIN:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
263 /* V.34 support is a work in progress. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
264 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
265 default:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
266 front_end_status(s, T30_FRONT_END_SIGNAL_ABSENT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
267 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
268 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
269 /*endswitch*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
270 fe->hdlc_rx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
271 fe->rx_data_missing = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
272 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
273 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
274 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
275
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
276 static int fake_rx_indicator(t38_core_state_t *t, t38_terminal_state_t *s, int indicator)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
277 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
278 int ret;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
279
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
280 ret = process_rx_indicator(t, s, indicator);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
281 t->current_rx_indicator = indicator;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
282 return ret;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
283 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
284 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
285
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
286 static int process_rx_data(t38_core_state_t *t, void *user_data, int data_type, int field_type, const uint8_t *buf, int len)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
287 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
288 t38_terminal_state_t *s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
289 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
290 #if defined(_MSC_VER)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
291 uint8_t *buf2 = (uint8_t *) _alloca(len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
292 #else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
293 uint8_t buf2[len];
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
294 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
295
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
296 s = (t38_terminal_state_t *) user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
297 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
298 /* In termination mode we don't care very much what the data type is apart from a couple of
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
299 special cases. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
300 switch (data_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
301 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
302 case T38_DATA_V8:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
303 switch (field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
304 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
305 case T38_FIELD_CM_MESSAGE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
306 if (len >= 1)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
307 span_log(&s->logging, SPAN_LOG_FLOW, "CM profile %d - %s\n", buf[0] - '0', t38_cm_profile_to_str(buf[0]));
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
308 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
309 span_log(&s->logging, SPAN_LOG_FLOW, "Bad length for CM message - %d\n", len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
310 //front_end_status(s, T30_FRONT_END_RECEIVE_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
311 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
312 case T38_FIELD_JM_MESSAGE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
313 if (len >= 2)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
314 span_log(&s->logging, SPAN_LOG_FLOW, "JM - %s\n", t38_jm_to_str(buf, len));
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
315 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
316 span_log(&s->logging, SPAN_LOG_FLOW, "Bad length for JM message - %d\n", len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
317 //front_end_status(s, T30_FRONT_END_RECEIVE_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
318 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
319 case T38_FIELD_CI_MESSAGE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
320 if (len >= 1)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
321 span_log(&s->logging, SPAN_LOG_FLOW, "CI 0x%X\n", buf[0]);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
322 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
323 span_log(&s->logging, SPAN_LOG_FLOW, "Bad length for CI message - %d\n", len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
324 //front_end_status(s, T30_FRONT_END_RECEIVE_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
325 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
326 default:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
327 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
328 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
329 /*endswitch*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
330 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
331 case T38_DATA_V34_PRI_RATE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
332 switch (field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
333 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
334 case T38_FIELD_V34RATE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
335 if (len >= 3)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
336 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
337 /* Just get and store the rate. The front end has no real interest in the
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
338 actual bit rate. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
339 fe->t38.v34_rate = t38_v34rate_to_bps(buf, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
340 span_log(&s->logging, SPAN_LOG_FLOW, "V.34 rate %d bps\n", fe->t38.v34_rate);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
341 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
342 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
343 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
344 span_log(&s->logging, SPAN_LOG_FLOW, "Bad length for V34rate message - %d\n", len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
345 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
346 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
347 default:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
348 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
349 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
350 /*endswitch*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
351 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
352 default:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
353 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
354 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
355 /*endswitch*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
356 switch (field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
357 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
358 case T38_FIELD_HDLC_DATA:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
359 if (fe->timeout_rx_samples == 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
360 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
361 /* HDLC can just start without any signal indicator on some platforms, even when
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
362 there is zero packet lost. Nasty, but true. Its a good idea to be tolerant of
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
363 loss, though, so accepting a sudden start of HDLC data is the right thing to do. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
364 fake_rx_indicator(t, s, T38_IND_V21_PREAMBLE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
365 /* All real HDLC messages in the FAX world start with 0xFF. If this one is not starting
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
366 with 0xFF it would appear some octets must have been missed before this one. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
367 if (len <= 0 || buf[0] != 0xFF)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
368 fe->rx_data_missing = TRUE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
369 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
370 if (len > 0 && fe->hdlc_rx.len + len <= T38_MAX_HDLC_LEN)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
371 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
372 bit_reverse(fe->hdlc_rx.buf + fe->hdlc_rx.len, buf, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
373 fe->hdlc_rx.len += len;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
374 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
375 fe->timeout_rx_samples = fe->samples + ms_to_samples(MID_RX_TIMEOUT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
376 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
377 case T38_FIELD_HDLC_FCS_OK:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
378 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
379 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
380 span_log(&s->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_OK!\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
381 /* The sender has incorrectly included data in this message. It is unclear what we should do
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
382 with it, to maximise tolerance of buggy implementations. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
383 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
384 /* Some T.38 implementations send multiple T38_FIELD_HDLC_FCS_OK messages, in IFP packets with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
385 incrementing sequence numbers, which are actually repeats. They get through to this point because
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
386 of the incrementing sequence numbers. We need to filter them here in a context sensitive manner. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
387 if (t->current_rx_data_type != data_type || t->current_rx_field_type != field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
388 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
389 span_log(&s->logging, SPAN_LOG_FLOW, "Type %s - CRC OK (%s)\n", (fe->hdlc_rx.len >= 3) ? t30_frametype(fe->hdlc_rx.buf[2]) : "???", (fe->rx_data_missing) ? "missing octets" : "clean");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
390 hdlc_accept_frame(s, fe->hdlc_rx.buf, fe->hdlc_rx.len, !fe->rx_data_missing);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
391 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
392 fe->hdlc_rx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
393 fe->rx_data_missing = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
394 fe->timeout_rx_samples = fe->samples + ms_to_samples(MID_RX_TIMEOUT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
395 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
396 case T38_FIELD_HDLC_FCS_BAD:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
397 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
398 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
399 span_log(&s->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_BAD!\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
400 /* The sender has incorrectly included data in this message. We can safely ignore it, as the
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
401 bad FCS means we will throw away the whole message, anyway. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
402 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
403 /* Some T.38 implementations send multiple T38_FIELD_HDLC_FCS_BAD messages, in IFP packets with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
404 incrementing sequence numbers, which are actually repeats. They get through to this point because
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
405 of the incrementing sequence numbers. We need to filter them here in a context sensitive manner. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
406 if (t->current_rx_data_type != data_type || t->current_rx_field_type != field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
407 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
408 span_log(&s->logging, SPAN_LOG_FLOW, "Type %s - CRC bad (%s)\n", (fe->hdlc_rx.len >= 3) ? t30_frametype(fe->hdlc_rx.buf[2]) : "???", (fe->rx_data_missing) ? "missing octets" : "clean");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
409 hdlc_accept_frame(s, fe->hdlc_rx.buf, fe->hdlc_rx.len, FALSE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
410 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
411 fe->hdlc_rx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
412 fe->rx_data_missing = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
413 fe->timeout_rx_samples = fe->samples + ms_to_samples(MID_RX_TIMEOUT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
414 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
415 case T38_FIELD_HDLC_FCS_OK_SIG_END:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
416 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
417 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
418 span_log(&s->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_OK_SIG_END!\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
419 /* The sender has incorrectly included data in this message. It is unclear what we should do
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
420 with it, to maximise tolerance of buggy implementations. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
421 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
422 /* Some T.38 implementations send multiple T38_FIELD_HDLC_FCS_OK_SIG_END messages, in IFP packets with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
423 incrementing sequence numbers, which are actually repeats. They get through to this point because
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
424 of the incrementing sequence numbers. We need to filter them here in a context sensitive manner. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
425 if (t->current_rx_data_type != data_type || t->current_rx_field_type != field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
426 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
427 span_log(&s->logging, SPAN_LOG_FLOW, "Type %s - CRC OK, sig end (%s)\n", (fe->hdlc_rx.len >= 3) ? t30_frametype(fe->hdlc_rx.buf[2]) : "???", (fe->rx_data_missing) ? "missing octets" : "clean");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
428 hdlc_accept_frame(s, fe->hdlc_rx.buf, fe->hdlc_rx.len, !fe->rx_data_missing);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
429 hdlc_accept_frame(s, NULL, SIG_STATUS_CARRIER_DOWN, TRUE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
430 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
431 fe->hdlc_rx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
432 fe->rx_data_missing = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
433 /* Treat this like a no signal indicator has occurred, so if the no signal indicator is missing, we are still OK */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
434 fake_rx_indicator(t, s, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
435 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
436 case T38_FIELD_HDLC_FCS_BAD_SIG_END:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
437 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
438 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
439 span_log(&s->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_BAD_SIG_END!\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
440 /* The sender has incorrectly included data in this message. We can safely ignore it, as the
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
441 bad FCS means we will throw away the whole message, anyway. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
442 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
443 /* Some T.38 implementations send multiple T38_FIELD_HDLC_FCS_BAD_SIG_END messages, in IFP packets with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
444 incrementing sequence numbers, which are actually repeats. They get through to this point because
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
445 of the incrementing sequence numbers. We need to filter them here in a context sensitive manner. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
446 if (t->current_rx_data_type != data_type || t->current_rx_field_type != field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
447 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
448 span_log(&s->logging, SPAN_LOG_FLOW, "Type %s - CRC bad, sig end (%s)\n", (fe->hdlc_rx.len >= 3) ? t30_frametype(fe->hdlc_rx.buf[2]) : "???", (fe->rx_data_missing) ? "missing octets" : "clean");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
449 hdlc_accept_frame(s, fe->hdlc_rx.buf, fe->hdlc_rx.len, FALSE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
450 hdlc_accept_frame(s, NULL, SIG_STATUS_CARRIER_DOWN, TRUE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
451 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
452 fe->hdlc_rx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
453 fe->rx_data_missing = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
454 /* Treat this like a no signal indicator has occurred, so if the no signal indicator is missing, we are still OK */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
455 fake_rx_indicator(t, s, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
456 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
457 case T38_FIELD_HDLC_SIG_END:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
458 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
459 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
460 span_log(&s->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_SIG_END!\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
461 /* The sender has incorrectly included data in this message, but there seems nothing meaningful
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
462 it could be. There could not be an FCS good/bad report beyond this. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
463 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
464 /* Some T.38 implementations send multiple T38_FIELD_HDLC_SIG_END messages, in IFP packets with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
465 incrementing sequence numbers, which are actually repeats. They get through to this point because
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
466 of the incrementing sequence numbers. We need to filter them here in a context sensitive manner. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
467 if (t->current_rx_data_type != data_type || t->current_rx_field_type != field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
468 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
469 /* WORKAROUND: At least some Mediatrix boxes have a bug, where they can send this message at the
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
470 end of non-ECM data. We need to tolerate this. We use the generic receive complete
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
471 indication, rather than the specific HDLC carrier down. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
472 /* This message is expected under 2 circumstances. One is as an alternative to T38_FIELD_HDLC_FCS_OK_SIG_END -
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
473 i.e. they send T38_FIELD_HDLC_FCS_OK, and then T38_FIELD_HDLC_SIG_END when the carrier actually drops.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
474 The other is because the HDLC signal drops unexpectedly - i.e. not just after a final frame. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
475 fe->hdlc_rx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
476 fe->rx_data_missing = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
477 front_end_status(s, T30_FRONT_END_RECEIVE_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
478 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
479 /* Treat this like a no signal indicator has occurred, so if the no signal indicator is missing, we are still OK */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
480 fake_rx_indicator(t, s, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
481 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
482 case T38_FIELD_T4_NON_ECM_DATA:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
483 if (!fe->rx_signal_present)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
484 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
485 t30_non_ecm_put_bit(&s->t30, SIG_STATUS_TRAINING_SUCCEEDED);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
486 fe->rx_signal_present = TRUE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
487 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
488 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
489 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
490 bit_reverse(buf2, buf, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
491 t30_non_ecm_put_chunk(&s->t30, buf2, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
492 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
493 fe->timeout_rx_samples = fe->samples + ms_to_samples(MID_RX_TIMEOUT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
494 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
495 case T38_FIELD_T4_NON_ECM_SIG_END:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
496 /* Some T.38 implementations send multiple T38_FIELD_T4_NON_ECM_SIG_END messages, in IFP packets with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
497 incrementing sequence numbers, which are actually repeats. They get through to this point because
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
498 of the incrementing sequence numbers. We need to filter them here in a context sensitive manner. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
499 if (t->current_rx_data_type != data_type || t->current_rx_field_type != field_type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
500 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
501 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
502 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
503 if (!fe->rx_signal_present)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
504 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
505 t30_non_ecm_put_bit(&s->t30, SIG_STATUS_TRAINING_SUCCEEDED);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
506 fe->rx_signal_present = TRUE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
507 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
508 bit_reverse(buf2, buf, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
509 t30_non_ecm_put_chunk(&s->t30, buf2, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
510 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
511 /* WORKAROUND: At least some Mediatrix boxes have a bug, where they can send HDLC signal end where
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
512 they should send non-ECM signal end. It is possible they also do the opposite.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
513 We need to tolerate this, so we use the generic receive complete
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
514 indication, rather than the specific non-ECM carrier down. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
515 front_end_status(s, T30_FRONT_END_RECEIVE_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
516 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
517 fe->rx_signal_present = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
518 /* Treat this like a no signal indicator has occurred, so if the no signal indicator is missing, we are still OK */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
519 fake_rx_indicator(t, s, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
520 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
521 default:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
522 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
523 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
524 /*endswitch*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
525 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
526 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
527 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
528
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
529 static void send_hdlc(void *user_data, const uint8_t *msg, int len)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
530 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
531 t38_terminal_state_t *s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
532
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
533 s = (t38_terminal_state_t *) user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
534 if (len <= 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
535 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
536 s->t38_fe.hdlc_tx.len = -1;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
537 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
538 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
539 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
540 s->t38_fe.hdlc_tx.extra_bits = extra_bits_in_stuffed_frame(msg, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
541 bit_reverse(s->t38_fe.hdlc_tx.buf, msg, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
542 s->t38_fe.hdlc_tx.len = len;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
543 s->t38_fe.hdlc_tx.ptr = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
544 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
545 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
546 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
547
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
548 static __inline__ int bits_to_us(t38_terminal_state_t *s, int bits)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
549 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
550 if (s->t38_fe.ms_per_tx_chunk == 0 || s->t38_fe.tx_bit_rate == 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
551 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
552 return bits*1000000/s->t38_fe.tx_bit_rate;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
553 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
554 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
555
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
556 static void set_octets_per_data_packet(t38_terminal_state_t *s, int bit_rate)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
557 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
558 s->t38_fe.tx_bit_rate = bit_rate;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
559 if (s->t38_fe.ms_per_tx_chunk)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
560 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
561 s->t38_fe.octets_per_data_packet = s->t38_fe.ms_per_tx_chunk*bit_rate/(8*1000);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
562 /* Make sure we have a positive number (i.e. we didn't truncate to zero). */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
563 if (s->t38_fe.octets_per_data_packet < 1)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
564 s->t38_fe.octets_per_data_packet = 1;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
565 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
566 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
567 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
568 s->t38_fe.octets_per_data_packet = MAX_OCTETS_PER_UNPACED_CHUNK;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
569 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
570 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
571 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
572
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
573 static int stream_non_ecm(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
574 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
575 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
576 uint8_t buf[MAX_OCTETS_PER_UNPACED_CHUNK + 50];
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
577 int delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
578 int len;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
579
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
580 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
581 for (delay = 0; delay == 0; )
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
582 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
583 switch (fe->timed_step)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
584 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
585 case T38_TIMED_STEP_NON_ECM_MODEM:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
586 /* Create a 75ms silence */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
587 if (fe->t38.current_tx_indicator != T38_IND_NO_SIGNAL)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
588 delay = t38_core_send_indicator(&fe->t38, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
589 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
590 delay = 75000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
591 fe->timed_step = T38_TIMED_STEP_NON_ECM_MODEM_2;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
592 fe->next_tx_samples = fe->samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
593 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
594 case T38_TIMED_STEP_NON_ECM_MODEM_2:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
595 /* Switch on a fast modem, and give the training time to complete */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
596 delay = t38_core_send_indicator(&fe->t38, fe->next_tx_indicator);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
597 fe->timed_step = T38_TIMED_STEP_NON_ECM_MODEM_3;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
598 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
599 case T38_TIMED_STEP_NON_ECM_MODEM_3:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
600 /* Send a chunk of non-ECM image data */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
601 /* T.38 says it is OK to send the last of the non-ECM data in the signal end message.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
602 However, I think the early versions of T.38 said the signal end message should not
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
603 contain data. Hopefully, following the current spec will not cause compatibility
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
604 issues. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
605 len = t30_non_ecm_get_chunk(&s->t30, buf, fe->octets_per_data_packet);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
606 if (len > 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
607 bit_reverse(buf, buf, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
608 if (len < fe->octets_per_data_packet)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
609 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
610 /* That's the end of the image data. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
611 if (s->t38_fe.ms_per_tx_chunk)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
612 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
613 /* Pad the end of the data with some zeros. If we just stop abruptly
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
614 at the end of the EOLs, some ATAs fail to clean up properly before
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
615 shutting down their transmit modem, and the last few rows of the image
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
616 are lost or corrupted. Simply delaying the no-signal message does not
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
617 help for all implentations. It is usually ignored, which is probably
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
618 the right thing to do after receiving a message saying the signal has
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
619 ended. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
620 memset(buf + len, 0, fe->octets_per_data_packet - len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
621 fe->non_ecm_trailer_bytes = 3*fe->octets_per_data_packet + len;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
622 len = fe->octets_per_data_packet;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
623 fe->timed_step = T38_TIMED_STEP_NON_ECM_MODEM_4;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
624 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
625 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
626 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
627 /* If we are sending quickly there seems no point in doing any padding */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
628 t38_core_send_data(&fe->t38, fe->current_tx_data_type, T38_FIELD_T4_NON_ECM_SIG_END, buf, len, T38_PACKET_CATEGORY_IMAGE_DATA_END);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
629 fe->timed_step = T38_TIMED_STEP_NON_ECM_MODEM_5;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
630 delay = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
631 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
632 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
633 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
634 t38_core_send_data(&fe->t38, fe->current_tx_data_type, T38_FIELD_T4_NON_ECM_DATA, buf, len, T38_PACKET_CATEGORY_IMAGE_DATA);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
635 delay = bits_to_us(s, 8*len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
636 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
637 case T38_TIMED_STEP_NON_ECM_MODEM_4:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
638 /* Send padding */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
639 len = fe->octets_per_data_packet;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
640 fe->non_ecm_trailer_bytes -= fe->octets_per_data_packet;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
641 if (fe->non_ecm_trailer_bytes <= 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
642 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
643 len += fe->non_ecm_trailer_bytes;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
644 memset(buf, 0, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
645 t38_core_send_data(&fe->t38, fe->current_tx_data_type, T38_FIELD_T4_NON_ECM_SIG_END, buf, len, T38_PACKET_CATEGORY_IMAGE_DATA_END);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
646 fe->timed_step = T38_TIMED_STEP_NON_ECM_MODEM_5;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
647 /* Allow a bit more time than the data will take to play out, to ensure the far ATA does not
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
648 cut things short. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
649 delay = bits_to_us(s, 8*len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
650 if (s->t38_fe.ms_per_tx_chunk)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
651 delay += 60000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
652 front_end_status(s, T30_FRONT_END_SEND_STEP_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
653 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
654 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
655 memset(buf, 0, len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
656 t38_core_send_data(&fe->t38, fe->current_tx_data_type, T38_FIELD_T4_NON_ECM_DATA, buf, len, T38_PACKET_CATEGORY_IMAGE_DATA);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
657 delay = bits_to_us(s, 8*len);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
658 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
659 case T38_TIMED_STEP_NON_ECM_MODEM_5:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
660 /* This should not be needed, since the message above indicates the end of the signal, but it
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
661 seems like it can improve compatibility with quirky implementations. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
662 delay = t38_core_send_indicator(&fe->t38, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
663 fe->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
664 return delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
665 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
666 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
667 return delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
668 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
669 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
670
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
671 static int stream_hdlc(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
672 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
673 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
674 uint8_t buf[MAX_OCTETS_PER_UNPACED_CHUNK + 50];
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
675 t38_data_field_t data_fields[2];
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
676 int category;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
677 int previous;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
678 int delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
679 int i;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
680
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
681 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
682 for (delay = 0; delay == 0; )
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
683 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
684 switch (fe->timed_step)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
685 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
686 case T38_TIMED_STEP_HDLC_MODEM:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
687 /* Create a 75ms silence */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
688 if (fe->t38.current_tx_indicator != T38_IND_NO_SIGNAL)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
689 delay = t38_core_send_indicator(&fe->t38, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
690 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
691 delay = 75000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
692 fe->timed_step = T38_TIMED_STEP_HDLC_MODEM_2;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
693 fe->next_tx_samples = fe->samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
694 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
695 case T38_TIMED_STEP_HDLC_MODEM_2:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
696 /* Send HDLC preambling */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
697 delay = t38_core_send_indicator(&fe->t38, fe->next_tx_indicator);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
698 delay += t38_core_send_flags_delay(&fe->t38, fe->next_tx_indicator);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
699 fe->timed_step = T38_TIMED_STEP_HDLC_MODEM_3;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
700 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
701 case T38_TIMED_STEP_HDLC_MODEM_3:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
702 /* Send a chunk of HDLC data */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
703 i = fe->hdlc_tx.len - fe->hdlc_tx.ptr;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
704 if (fe->octets_per_data_packet >= i)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
705 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
706 /* The last part of an HDLC frame */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
707 if (fe->chunking_modes & T38_CHUNKING_MERGE_FCS_WITH_DATA)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
708 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
709 /* Copy the data, as we might be about to refill the buffer it is in */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
710 memcpy(buf, &fe->hdlc_tx.buf[fe->hdlc_tx.ptr], i);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
711 data_fields[0].field_type = T38_FIELD_HDLC_DATA;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
712 data_fields[0].field = buf;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
713 data_fields[0].field_len = i;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
714
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
715 /* Now see about the next HDLC frame. This will tell us whether to send FCS_OK or FCS_OK_SIG_END */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
716 previous = fe->current_tx_data_type;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
717 fe->hdlc_tx.ptr = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
718 fe->hdlc_tx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
719 front_end_status(s, T30_FRONT_END_SEND_STEP_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
720 /* The above step should have got the next HDLC step ready - either another frame, or an instruction to stop transmission. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
721 if (fe->hdlc_tx.len < 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
722 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
723 data_fields[1].field_type = T38_FIELD_HDLC_FCS_OK_SIG_END;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
724 data_fields[1].field = NULL;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
725 data_fields[1].field_len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
726 category = (s->t38_fe.current_tx_data_type == T38_DATA_V21) ? T38_PACKET_CATEGORY_CONTROL_DATA_END : T38_PACKET_CATEGORY_IMAGE_DATA_END;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
727 t38_core_send_data_multi_field(&fe->t38, fe->current_tx_data_type, data_fields, 2, category);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
728 fe->timed_step = T38_TIMED_STEP_HDLC_MODEM_5;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
729 /* We add a bit of extra time here, as with some implementations
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
730 the carrier falling too abruptly causes data loss. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
731 delay = bits_to_us(s, i*8 + fe->hdlc_tx.extra_bits);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
732 if (s->t38_fe.ms_per_tx_chunk)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
733 delay += 100000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
734 front_end_status(s, T30_FRONT_END_SEND_STEP_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
735 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
736 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
737 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
738 data_fields[1].field_type = T38_FIELD_HDLC_FCS_OK;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
739 data_fields[1].field = NULL;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
740 data_fields[1].field_len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
741 category = (s->t38_fe.current_tx_data_type == T38_DATA_V21) ? T38_PACKET_CATEGORY_CONTROL_DATA : T38_PACKET_CATEGORY_IMAGE_DATA;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
742 t38_core_send_data_multi_field(&fe->t38, fe->current_tx_data_type, data_fields, 2, category);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
743 fe->timed_step = T38_TIMED_STEP_HDLC_MODEM_3;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
744 delay = bits_to_us(s, i*8 + fe->hdlc_tx.extra_bits);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
745 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
746 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
747 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
748 category = (s->t38_fe.current_tx_data_type == T38_DATA_V21) ? T38_PACKET_CATEGORY_CONTROL_DATA : T38_PACKET_CATEGORY_IMAGE_DATA;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
749 t38_core_send_data(&fe->t38, fe->current_tx_data_type, T38_FIELD_HDLC_DATA, &fe->hdlc_tx.buf[fe->hdlc_tx.ptr], i, category);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
750 fe->timed_step = T38_TIMED_STEP_HDLC_MODEM_4;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
751 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
752 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
753 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
754 i = fe->octets_per_data_packet;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
755 category = (s->t38_fe.current_tx_data_type == T38_DATA_V21) ? T38_PACKET_CATEGORY_CONTROL_DATA : T38_PACKET_CATEGORY_IMAGE_DATA;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
756 t38_core_send_data(&fe->t38, fe->current_tx_data_type, T38_FIELD_HDLC_DATA, &fe->hdlc_tx.buf[fe->hdlc_tx.ptr], i, category);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
757 fe->hdlc_tx.ptr += i;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
758 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
759 delay = bits_to_us(s, i*8);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
760 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
761 case T38_TIMED_STEP_HDLC_MODEM_4:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
762 /* End of HDLC frame */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
763 previous = fe->current_tx_data_type;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
764 fe->hdlc_tx.ptr = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
765 fe->hdlc_tx.len = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
766 front_end_status(s, T30_FRONT_END_SEND_STEP_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
767 /* The above step should have got the next HDLC step ready - either another frame, or an instruction to stop transmission. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
768 if (fe->hdlc_tx.len < 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
769 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
770 /* End of transmission */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
771 category = (s->t38_fe.current_tx_data_type == T38_DATA_V21) ? T38_PACKET_CATEGORY_CONTROL_DATA_END : T38_PACKET_CATEGORY_IMAGE_DATA_END;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
772 t38_core_send_data(&fe->t38, previous, T38_FIELD_HDLC_FCS_OK_SIG_END, NULL, 0, category);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
773 fe->timed_step = T38_TIMED_STEP_HDLC_MODEM_5;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
774 /* We add a bit of extra time here, as with some implementations
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
775 the carrier falling too abruptly causes data loss. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
776 delay = bits_to_us(s, fe->hdlc_tx.extra_bits);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
777 if (s->t38_fe.ms_per_tx_chunk)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
778 delay += 100000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
779 front_end_status(s, T30_FRONT_END_SEND_STEP_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
780 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
781 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
782 if (fe->hdlc_tx.len == 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
783 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
784 /* Now, how did we get here? We have finished a frame, but have no new frame to
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
785 send, and no end of transmission condition. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
786 span_log(&s->logging, SPAN_LOG_FLOW, "No new frame or end transmission condition.\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
787 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
788 /* Finish the current frame off, and prepare for the next one. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
789 category = (s->t38_fe.current_tx_data_type == T38_DATA_V21) ? T38_PACKET_CATEGORY_CONTROL_DATA : T38_PACKET_CATEGORY_IMAGE_DATA;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
790 t38_core_send_data(&fe->t38, previous, T38_FIELD_HDLC_FCS_OK, NULL, 0, category);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
791 fe->timed_step = T38_TIMED_STEP_HDLC_MODEM_3;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
792 /* We should now wait enough time for everything to clear through an analogue modem at the far end. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
793 delay = bits_to_us(s, fe->hdlc_tx.extra_bits);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
794 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
795 case T38_TIMED_STEP_HDLC_MODEM_5:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
796 /* Note that some boxes do not like us sending a T38_FIELD_HDLC_SIG_END at this point.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
797 A T38_IND_NO_SIGNAL should always be OK. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
798 delay = t38_core_send_indicator(&fe->t38, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
799 fe->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
800 return delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
801 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
802 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
803 return delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
804 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
805 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
806
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
807 static int stream_ced(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
808 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
809 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
810 int delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
811
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
812 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
813 for (delay = 0; delay == 0; )
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
814 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
815 switch (fe->timed_step)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
816 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
817 case T38_TIMED_STEP_CED:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
818 /* It seems common practice to start with a no signal indicator, though
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
819 this is not a specified requirement. Since we should be sending 200ms
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
820 of silence, starting the delay with a no signal indication makes sense.
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
821 We do need a 200ms delay, as that is a specification requirement. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
822 fe->timed_step = T38_TIMED_STEP_CED_2;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
823 delay = t38_core_send_indicator(&fe->t38, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
824 delay = 200000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
825 fe->next_tx_samples = fe->samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
826 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
827 case T38_TIMED_STEP_CED_2:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
828 /* Initial 200ms delay over. Send the CED indicator */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
829 fe->timed_step = T38_TIMED_STEP_CED_3;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
830 delay = t38_core_send_indicator(&fe->t38, T38_IND_CED);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
831 fe->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
832 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
833 case T38_TIMED_STEP_CED_3:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
834 /* End of CED */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
835 fe->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
836 front_end_status(s, T30_FRONT_END_SEND_STEP_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
837 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
838 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
839 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
840 return delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
841 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
842 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
843
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
844 static int stream_cng(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
845 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
846 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
847 int delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
848
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
849 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
850 for (delay = 0; delay == 0; )
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
851 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
852 switch (fe->timed_step)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
853 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
854 case T38_TIMED_STEP_CNG:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
855 /* It seems common practice to start with a no signal indicator, though
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
856 this is not a specified requirement of the T.38 spec. Since we should
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
857 be sending 200ms of silence, according to T.30, starting that delay with
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
858 a no signal indication makes sense. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
859 fe->timed_step = T38_TIMED_STEP_CNG_2;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
860 delay = t38_core_send_indicator(&fe->t38, T38_IND_NO_SIGNAL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
861 delay = 200000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
862 fe->next_tx_samples = fe->samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
863 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
864 case T38_TIMED_STEP_CNG_2:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
865 /* Initial short delay over. Send the CNG indicator. CNG persists until something
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
866 coming the other way interrupts it, or a long timeout controlled by the T.30 engine
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
867 expires. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
868 fe->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
869 delay = t38_core_send_indicator(&fe->t38, T38_IND_CNG);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
870 fe->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
871 return delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
872 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
873 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
874 return delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
875 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
876 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
877
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
878 SPAN_DECLARE(int) t38_terminal_send_timeout(t38_terminal_state_t *s, int samples)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
879 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
880 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
881 int delay;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
882
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
883 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
884 if (fe->current_rx_type == T30_MODEM_DONE || fe->current_tx_type == T30_MODEM_DONE)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
885 return TRUE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
886
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
887 fe->samples += samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
888 t30_timer_update(&s->t30, samples);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
889 if (fe->timeout_rx_samples && fe->samples > fe->timeout_rx_samples)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
890 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
891 span_log(&s->logging, SPAN_LOG_FLOW, "Timeout mid-receive\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
892 fe->timeout_rx_samples = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
893 front_end_status(s, T30_FRONT_END_RECEIVE_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
894 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
895 if (fe->timed_step == T38_TIMED_STEP_NONE)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
896 return FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
897 /* Wait until the right time comes along, unless we are working in "no delays" mode, while talking to an
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
898 IAF terminal. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
899 if (fe->ms_per_tx_chunk && fe->samples < fe->next_tx_samples)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
900 return FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
901 /* Its time to send something */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
902 delay = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
903 switch (fe->timed_step & 0xFFF0)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
904 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
905 case T38_TIMED_STEP_NON_ECM_MODEM:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
906 delay = stream_non_ecm(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
907 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
908 case T38_TIMED_STEP_HDLC_MODEM:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
909 delay = stream_hdlc(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
910 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
911 case T38_TIMED_STEP_CED:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
912 delay = stream_ced(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
913 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
914 case T38_TIMED_STEP_CNG:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
915 delay = stream_cng(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
916 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
917 case T38_TIMED_STEP_PAUSE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
918 /* End of timed pause */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
919 fe->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
920 front_end_status(s, T30_FRONT_END_SEND_STEP_COMPLETE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
921 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
922 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
923 fe->next_tx_samples += us_to_samples(delay);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
924 return FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
925 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
926 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
927
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
928 static void set_rx_type(void *user_data, int type, int bit_rate, int short_train, int use_hdlc)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
929 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
930 t38_terminal_state_t *s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
931
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
932 s = (t38_terminal_state_t *) user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
933 span_log(&s->logging, SPAN_LOG_FLOW, "Set rx type %d\n", type);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
934 s->t38_fe.current_rx_type = type;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
935 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
936 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
937
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
938 static void start_tx(t38_terminal_front_end_state_t *fe, int use_hdlc)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
939 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
940 /* The actual transmission process depends on whether we are sending at a paced manner,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
941 for interaction with a traditional FAX machine, or streaming as fast as we can, normally
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
942 over a TCP connection to a machine directly connected to the internet. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
943 if (fe->ms_per_tx_chunk)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
944 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
945 /* Start the paced packet transmission process. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
946 fe->timed_step = (use_hdlc) ? T38_TIMED_STEP_HDLC_MODEM : T38_TIMED_STEP_NON_ECM_MODEM;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
947 if (fe->next_tx_samples < fe->samples)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
948 fe->next_tx_samples = fe->samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
949 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
950 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
951 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
952 /* Start the fast streaming transmission process. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
953 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
954 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
955 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
956
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
957 static void set_tx_type(void *user_data, int type, int bit_rate, int short_train, int use_hdlc)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
958 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
959 t38_terminal_state_t *s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
960 t38_terminal_front_end_state_t *fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
961
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
962 s = (t38_terminal_state_t *) user_data;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
963 fe = &s->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
964 span_log(&s->logging, SPAN_LOG_FLOW, "Set tx type %d\n", type);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
965 if (fe->current_tx_type == type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
966 return;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
967
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
968 set_octets_per_data_packet(s, bit_rate);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
969 switch (type)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
970 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
971 case T30_MODEM_NONE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
972 /* If a "no signal" indicator is waiting to be played out, don't disturb it. */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
973 if (fe->timed_step != T38_TIMED_STEP_NON_ECM_MODEM_5 && fe->timed_step != T38_TIMED_STEP_HDLC_MODEM_5)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
974 fe->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
975 fe->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
976 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
977 case T30_MODEM_PAUSE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
978 fe->next_tx_samples = fe->samples + ms_to_samples(short_train);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
979 fe->timed_step = T38_TIMED_STEP_PAUSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
980 fe->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
981 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
982 case T30_MODEM_CED:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
983 fe->next_tx_samples = fe->samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
984 fe->timed_step = T38_TIMED_STEP_CED;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
985 fe->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
986 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
987 case T30_MODEM_CNG:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
988 fe->next_tx_samples = fe->samples;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
989 fe->timed_step = T38_TIMED_STEP_CNG;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
990 fe->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
991 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
992 case T30_MODEM_V21:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
993 fe->next_tx_indicator = T38_IND_V21_PREAMBLE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
994 fe->current_tx_data_type = T38_DATA_V21;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
995 start_tx(fe, use_hdlc);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
996 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
997 case T30_MODEM_V27TER:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
998 switch (bit_rate)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
999 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1000 case 2400:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1001 fe->next_tx_indicator = T38_IND_V27TER_2400_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1002 fe->current_tx_data_type = T38_DATA_V27TER_2400;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1003 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1004 case 4800:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1005 fe->next_tx_indicator = T38_IND_V27TER_4800_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1006 fe->current_tx_data_type = T38_DATA_V27TER_4800;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1007 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1008 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1009 start_tx(fe, use_hdlc);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1010 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1011 case T30_MODEM_V29:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1012 switch (bit_rate)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1013 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1014 case 7200:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1015 fe->next_tx_indicator = T38_IND_V29_7200_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1016 fe->current_tx_data_type = T38_DATA_V29_7200;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1017 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1018 case 9600:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1019 fe->next_tx_indicator = T38_IND_V29_9600_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1020 fe->current_tx_data_type = T38_DATA_V29_9600;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1021 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1022 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1023 start_tx(fe, use_hdlc);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1024 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1025 case T30_MODEM_V17:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1026 switch (bit_rate)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1027 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1028 case 7200:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1029 fe->next_tx_indicator = (short_train) ? T38_IND_V17_7200_SHORT_TRAINING : T38_IND_V17_7200_LONG_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1030 fe->current_tx_data_type = T38_DATA_V17_7200;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1031 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1032 case 9600:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1033 fe->next_tx_indicator = (short_train) ? T38_IND_V17_9600_SHORT_TRAINING : T38_IND_V17_9600_LONG_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1034 fe->current_tx_data_type = T38_DATA_V17_9600;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1035 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1036 case 12000:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1037 fe->next_tx_indicator = (short_train) ? T38_IND_V17_12000_SHORT_TRAINING : T38_IND_V17_12000_LONG_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1038 fe->current_tx_data_type = T38_DATA_V17_12000;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1039 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1040 case 14400:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1041 fe->next_tx_indicator = (short_train) ? T38_IND_V17_14400_SHORT_TRAINING : T38_IND_V17_14400_LONG_TRAINING;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1042 fe->current_tx_data_type = T38_DATA_V17_14400;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1043 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1044 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1045 start_tx(fe, use_hdlc);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1046 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1047 case T30_MODEM_DONE:
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1048 span_log(&s->logging, SPAN_LOG_FLOW, "FAX exchange complete\n");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1049 fe->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1050 fe->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1051 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1052 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1053 fe->current_tx_type = type;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1054 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1055 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1056
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1057 SPAN_DECLARE(void) t38_terminal_set_config(t38_terminal_state_t *s, int without_pacing)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1058 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1059 if (without_pacing)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1060 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1061 /* Continuous streaming mode, as used for TPKT over TCP transport */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1062 /* Inhibit indicator packets */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1063 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_INDICATOR, 0);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1064 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_CONTROL_DATA, 1);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1065 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_CONTROL_DATA_END, 1);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1066 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_IMAGE_DATA, 1);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1067 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_IMAGE_DATA_END, 1);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1068 s->t38_fe.ms_per_tx_chunk = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1069 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1070 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1071 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1072 /* Paced streaming mode, as used for UDP transports */
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1073 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_INDICATOR, INDICATOR_TX_COUNT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1074 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_CONTROL_DATA, DATA_TX_COUNT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1075 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_CONTROL_DATA_END, DATA_END_TX_COUNT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1076 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_IMAGE_DATA, DATA_TX_COUNT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1077 t38_set_redundancy_control(&s->t38_fe.t38, T38_PACKET_CATEGORY_IMAGE_DATA_END, DATA_END_TX_COUNT);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1078 s->t38_fe.ms_per_tx_chunk = MS_PER_TX_CHUNK;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1079 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1080 set_octets_per_data_packet(s, 300);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1081 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1082 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1083
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1084 SPAN_DECLARE(void) t38_terminal_set_tep_mode(t38_terminal_state_t *s, int use_tep)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1085 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1086 if (use_tep)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1087 s->t38_fe.chunking_modes |= T38_CHUNKING_ALLOW_TEP_TIME;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1088 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1089 s->t38_fe.chunking_modes &= ~T38_CHUNKING_ALLOW_TEP_TIME;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1090 t38_set_tep_handling(&s->t38_fe.t38, use_tep);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1091 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1092 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1093
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1094 SPAN_DECLARE(void) t38_terminal_set_fill_bit_removal(t38_terminal_state_t *s, int remove)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1095 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1096 if (remove)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1097 s->t38_fe.iaf |= T30_IAF_MODE_NO_FILL_BITS;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1098 else
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1099 s->t38_fe.iaf &= ~T30_IAF_MODE_NO_FILL_BITS;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1100 t30_set_iaf_mode(&s->t30, s->t38_fe.iaf);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1101 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1102 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1103
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1104 SPAN_DECLARE(t30_state_t *) t38_terminal_get_t30_state(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1105 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1106 return &s->t30;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1107 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1108 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1109
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1110 SPAN_DECLARE(t38_core_state_t *) t38_terminal_get_t38_core_state(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1111 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1112 return &s->t38_fe.t38;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1113 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1114 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1115
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1116 static int t38_terminal_t38_fe_init(t38_terminal_state_t *t,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1117 t38_tx_packet_handler_t *tx_packet_handler,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1118 void *tx_packet_user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1119 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1120 t38_terminal_front_end_state_t *s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1121
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1122 s = &t->t38_fe;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1123 t38_core_init(&s->t38,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1124 process_rx_indicator,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1125 process_rx_data,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1126 process_rx_missing,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1127 (void *) t,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1128 tx_packet_handler,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1129 tx_packet_user_data);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1130 t38_set_fastest_image_data_rate(&s->t38, 14400);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1131
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1132 s->rx_signal_present = FALSE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1133 s->timed_step = T38_TIMED_STEP_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1134 //s->iaf = T30_IAF_MODE_T37 | T30_IAF_MODE_T38;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1135 s->iaf = T30_IAF_MODE_T38;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1136
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1137 s->current_tx_data_type = T38_DATA_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1138 s->next_tx_samples = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1139 s->chunking_modes = T38_CHUNKING_ALLOW_TEP_TIME;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1140
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1141 s->hdlc_tx.ptr = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1142
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1143 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1144 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1145 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1146
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1147 SPAN_DECLARE(logging_state_t *) t38_terminal_get_logging_state(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1148 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1149 return &s->logging;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1150 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1151 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1152
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1153 SPAN_DECLARE(t38_terminal_state_t *) t38_terminal_init(t38_terminal_state_t *s,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1154 int calling_party,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1155 t38_tx_packet_handler_t *tx_packet_handler,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1156 void *tx_packet_user_data)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1157 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1158 if (tx_packet_handler == NULL)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1159 return NULL;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1160
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1161 if (s == NULL)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1162 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1163 if ((s = (t38_terminal_state_t *) malloc(sizeof(*s))) == NULL)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1164 return NULL;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1165 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1166 memset(s, 0, sizeof(*s));
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1167 span_log_init(&s->logging, SPAN_LOG_NONE, NULL);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1168 span_log_set_protocol(&s->logging, "T.38T");
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1169
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1170 t38_terminal_t38_fe_init(s, tx_packet_handler, tx_packet_user_data);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1171
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1172 t38_terminal_set_config(s, FALSE);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1173
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1174 t30_init(&s->t30,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1175 calling_party,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1176 set_rx_type,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1177 (void *) s,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1178 set_tx_type,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1179 (void *) s,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1180 send_hdlc,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1181 (void *) s);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1182 t30_set_iaf_mode(&s->t30, s->t38_fe.iaf);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1183 t30_set_supported_modems(&s->t30,
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1184 T30_SUPPORT_V27TER | T30_SUPPORT_V29 | T30_SUPPORT_V17 | T30_SUPPORT_IAF);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1185 t30_restart(&s->t30);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1186 return s;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1187 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1188 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1189
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1190 SPAN_DECLARE(int) t38_terminal_release(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1191 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1192 t30_release(&s->t30);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1193 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1194 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1195 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1196
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1197 SPAN_DECLARE(int) t38_terminal_free(t38_terminal_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1198 {
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1199 t38_terminal_release(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1200 free(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1201 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1202 }
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1203 /*- End of function --------------------------------------------------------*/
26cd8f1ef0b1 import spandsp-0.0.6pre17
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1204 /*- End of file ------------------------------------------------------------*/

Repositories maintained by Peter Meerwald, pmeerw@pmeerw.net.