annotate spandsp-0.0.3/spandsp-0.0.3/src/t31.c @ 5:f762bf195c4b

import spandsp-0.0.3
author Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date Fri, 25 Jun 2010 16:00:21 +0200
parents
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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5
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1 /*
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
2 * SpanDSP - a series of DSP components for telephony
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
3 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
4 * t31.c - A T.31 compatible class 1 FAX modem interface.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
5 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
6 * Written by Steve Underwood <steveu@coppice.org>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
7 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
8 * Special thanks to Lee Howard <faxguy@howardsilvan.com>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
9 * for his great work debugging and polishing this code.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
10 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
11 * Copyright (C) 2004, 2005, 2006 Steve Underwood
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
12 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
13 * All rights reserved.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
14 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
15 * This program is free software; you can redistribute it and/or modify
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
16 * it under the terms of the GNU General Public License version 2, as
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
17 * published by the Free Software Foundation.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
18 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
19 * This program is distributed in the hope that it will be useful,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
22 * GNU General Public License for more details.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
23 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
24 * You should have received a copy of the GNU General Public License
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
25 * along with this program; if not, write to the Free Software
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
27 *
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
28 * $Id: t31.c,v 1.83 2006/11/30 15:41:47 steveu Exp $
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
29 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
30
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
31 /*! \file */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
32
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
33 #ifdef HAVE_CONFIG_H
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
34 #include <config.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
35 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
36
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
37 #define _GNU_SOURCE
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
38
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
39 #include <inttypes.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
40 #include <stdlib.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
41 #include <stdio.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
42 #include <fcntl.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
43 #include <time.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
44 #include <memory.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
45 #include <string.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
46 #include <ctype.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
47 #if defined(HAVE_TGMATH_H)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
48 #include <tgmath.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
49 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
50 #if defined(HAVE_MATH_H)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
51 #include <math.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
52 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
53 #include <assert.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
54 #include <tiffio.h>
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
55
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
56 #include "spandsp/telephony.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
57 #include "spandsp/logging.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
58 #include "spandsp/bit_operations.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
59 #include "spandsp/dc_restore.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
60 #include "spandsp/queue.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
61 #include "spandsp/power_meter.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
62 #include "spandsp/complex.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
63 #include "spandsp/tone_generate.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
64 #include "spandsp/async.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
65 #include "spandsp/hdlc.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
66 #include "spandsp/silence_gen.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
67 #include "spandsp/fsk.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
68 #include "spandsp/v29rx.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
69 #include "spandsp/v29tx.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
70 #include "spandsp/v27ter_rx.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
71 #include "spandsp/v27ter_tx.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
72 #if defined(ENABLE_V17)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
73 #include "spandsp/v17rx.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
74 #include "spandsp/v17tx.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
75 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
76 #include "spandsp/t4.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
77 #include "spandsp/t30.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
78 #include "spandsp/t38_core.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
79
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
80 #include "spandsp/at_interpreter.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
81 #include "spandsp/t31.h"
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
82
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
83 #define MS_PER_TX_CHUNK 30
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
84 #define INDICATOR_TX_COUNT 4
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
85 #define DEFAULT_DTE_TIMEOUT 5
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
86
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
87 typedef const char *(*at_cmd_service_t)(t31_state_t *s, const char *cmd);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
88
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
89 #define ETX 0x03
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
90 #define DLE 0x10
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
91 #define SUB 0x1A
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
92
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
93 enum
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
94 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
95 T31_FLUSH,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
96 T31_SILENCE_TX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
97 T31_SILENCE_RX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
98 T31_CED_TONE,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
99 T31_CNG_TONE,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
100 T31_NOCNG_TONE,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
101 T31_V21_TX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
102 T31_V17_TX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
103 T31_V27TER_TX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
104 T31_V29_TX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
105 T31_V21_RX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
106 T31_V17_RX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
107 T31_V27TER_RX,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
108 T31_V29_RX
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
109 };
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
110
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
111 enum
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
112 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
113 T38_TIMED_STEP_NONE = 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
114 T38_TIMED_STEP_NON_ECM_MODEM,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
115 T38_TIMED_STEP_NON_ECM_MODEM_2,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
116 T38_TIMED_STEP_NON_ECM_MODEM_3,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
117 T38_TIMED_STEP_HDLC_MODEM,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
118 T38_TIMED_STEP_HDLC_MODEM_2,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
119 T38_TIMED_STEP_HDLC_MODEM_3,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
120 T38_TIMED_STEP_HDLC_MODEM_4,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
121 T38_TIMED_STEP_PAUSE
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
122 };
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
123
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
124 static int restart_modem(t31_state_t *s, int new_modem);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
125 static void hdlc_accept(void *user_data, int ok, const uint8_t *msg, int len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
126 #if defined(ENABLE_V17)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
127 static int early_v17_rx(void *user_data, const int16_t amp[], int len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
128 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
129 static int early_v27ter_rx(void *user_data, const int16_t amp[], int len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
130 static int early_v29_rx(void *user_data, const int16_t amp[], int len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
131 static int dummy_rx(void *s, const int16_t amp[], int len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
132 static int silence_rx(void *user_data, const int16_t amp[], int len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
133 static int cng_rx(void *user_data, const int16_t amp[], int len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
134
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
135 static __inline__ void t31_set_at_rx_mode(t31_state_t *s, int new_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
136 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
137 s->at_state.at_rx_mode = new_mode;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
138 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
139 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
140
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
141 static int process_rx_indicator(t38_core_state_t *s, void *user_data, int indicator)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
142 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
143 t31_state_t *t;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
144
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
145 t = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
146 switch (indicator)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
147 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
148 case T38_IND_NO_SIGNAL:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
149 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
150 case T38_IND_CNG:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
151 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
152 case T38_IND_CED:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
153 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
154 case T38_IND_V21_PREAMBLE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
155 t->hdlc_rx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
156 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
157 case T38_IND_V27TER_2400_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
158 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
159 case T38_IND_V27TER_4800_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
160 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
161 case T38_IND_V29_7200_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
162 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
163 case T38_IND_V29_9600_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
164 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
165 case T38_IND_V17_7200_SHORT_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
166 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
167 case T38_IND_V17_7200_LONG_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
168 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
169 case T38_IND_V17_9600_SHORT_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
170 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
171 case T38_IND_V17_9600_LONG_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
172 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
173 case T38_IND_V17_12000_SHORT_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
174 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
175 case T38_IND_V17_12000_LONG_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
176 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
177 case T38_IND_V17_14400_SHORT_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
178 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
179 case T38_IND_V17_14400_LONG_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
180 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
181 case T38_IND_V8_ANSAM:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
182 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
183 case T38_IND_V8_SIGNAL:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
184 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
185 case T38_IND_V34_CNTL_CHANNEL_1200:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
186 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
187 case T38_IND_V34_PRI_CHANNEL:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
188 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
189 case T38_IND_V34_CC_RETRAIN:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
190 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
191 case T38_IND_V33_12000_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
192 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
193 case T38_IND_V33_14400_TRAINING:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
194 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
195 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
196 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
197 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
198 t->missing_data = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
199 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
200 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
201 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
202
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
203 static int process_rx_data(t38_core_state_t *s, void *user_data, int data_type, int field_type, const uint8_t *buf, int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
204 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
205 t31_state_t *t;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
206 int i;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
207
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
208 t = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
209 switch (data_type)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
210 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
211 case T38_DATA_V21:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
212 case T38_DATA_V27TER_2400:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
213 case T38_DATA_V27TER_4800:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
214 case T38_DATA_V29_7200:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
215 case T38_DATA_V29_9600:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
216 case T38_DATA_V17_7200:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
217 case T38_DATA_V17_9600:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
218 case T38_DATA_V17_12000:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
219 case T38_DATA_V17_14400:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
220 case T38_DATA_V8:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
221 case T38_DATA_V34_PRI_RATE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
222 case T38_DATA_V34_CC_1200:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
223 case T38_DATA_V34_PRI_CH:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
224 case T38_DATA_V33_12000:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
225 case T38_DATA_V33_14400:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
226 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
227 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
228 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
229 switch (field_type)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
230 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
231 case T38_FIELD_HDLC_DATA:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
232 if (t->hdlc_rx_len + len <= 256 - 2)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
233 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
234 for (i = 0; i < len; i++)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
235 t->hdlc_rx_buf[t->hdlc_rx_len++] = bit_reverse8(buf[i]);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
236 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
237 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
238 case T38_FIELD_HDLC_FCS_OK:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
239 if (len > 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
240 span_log(&t->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_OK!\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
241 span_log(&t->logging, SPAN_LOG_FLOW, "Type %s - CRC OK (%s)\n", t30_frametype(t->tx_data[2]), (t->missing_data) ? "missing octets" : "clean");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
242 /* Don't deal with zero length frames. Some T.38 implementations send multiple T38_FIELD_HDLC_FCS_OK
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
243 packets, when they have sent no data for the body of the frame. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
244 if (t->current_rx_type == T31_V21_RX && t->tx_out_bytes > 0 && !t->missing_data)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
245 hdlc_accept((void *) t, TRUE, t->hdlc_rx_buf, t->hdlc_rx_len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
246 t->hdlc_rx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
247 t->missing_data = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
248 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
249 case T38_FIELD_HDLC_FCS_BAD:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
250 if (len > 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
251 span_log(&t->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_BAD!\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
252 span_log(&t->logging, SPAN_LOG_FLOW, "Type %s - CRC bad (%s)\n", t30_frametype(t->tx_data[2]), (t->missing_data) ? "missing octets" : "clean");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
253 t->hdlc_rx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
254 t->missing_data = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
255 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
256 case T38_FIELD_HDLC_FCS_OK_SIG_END:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
257 if (len > 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
258 span_log(&t->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_OK_SIG_END!\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
259 span_log(&t->logging, SPAN_LOG_FLOW, "Type %s - CRC OK, sig end (%s)\n", t30_frametype(t->tx_data[2]), (t->missing_data) ? "missing octets" : "clean");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
260 if (t->current_rx_type == T31_V21_RX)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
261 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
262 /* Don't deal with zero length frames. Some T.38 implementations send multiple T38_FIELD_HDLC_FCS_OK
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
263 packets, when they have sent no data for the body of the frame. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
264 if (t->tx_out_bytes > 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
265 hdlc_accept((void *) t, TRUE, t->hdlc_rx_buf, t->hdlc_rx_len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
266 hdlc_accept((void *) t, TRUE, NULL, PUTBIT_CARRIER_DOWN);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
267 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
268 t->tx_out_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
269 t->missing_data = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
270 t->hdlc_rx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
271 t->missing_data = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
272 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
273 case T38_FIELD_HDLC_FCS_BAD_SIG_END:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
274 if (len > 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
275 span_log(&t->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_FCS_BAD_SIG_END!\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
276 span_log(&t->logging, SPAN_LOG_FLOW, "Type %s - CRC bad, sig end (%s)\n", t30_frametype(t->tx_data[2]), (t->missing_data) ? "missing octets" : "clean");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
277 if (t->current_rx_type == T31_V21_RX)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
278 hdlc_accept((void *) t, TRUE, NULL, PUTBIT_CARRIER_DOWN);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
279 t->hdlc_rx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
280 t->missing_data = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
281 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
282 case T38_FIELD_HDLC_SIG_END:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
283 if (len > 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
284 span_log(&t->logging, SPAN_LOG_WARNING, "There is data in a T38_FIELD_HDLC_SIG_END!\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
285 /* This message is expected under 2 circumstances. One is as an alternative to T38_FIELD_HDLC_FCS_OK_SIG_END -
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
286 i.e. they send T38_FIELD_HDLC_FCS_OK, and then T38_FIELD_HDLC_SIG_END when the carrier actually drops.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
287 The other is because the HDLC signal drops unexpectedly - i.e. not just after a final frame. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
288 if (t->current_rx_type == T31_V21_RX)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
289 hdlc_accept((void *) t, TRUE, NULL, PUTBIT_CARRIER_DOWN);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
290 t->hdlc_rx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
291 t->missing_data = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
292 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
293 case T38_FIELD_T4_NON_ECM_DATA:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
294 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
295 case T38_FIELD_T4_NON_ECM_SIG_END:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
296 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
297 case T38_FIELD_CM_MESSAGE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
298 case T38_FIELD_JM_MESSAGE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
299 case T38_FIELD_CI_MESSAGE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
300 case T38_FIELD_V34RATE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
301 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
302 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
303 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
304 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
305 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
306 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
307
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
308 static int process_rx_missing(t38_core_state_t *s, void *user_data, int rx_seq_no, int expected_seq_no)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
309 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
310 t31_state_t *t;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
311
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
312 t = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
313 t->missing_data = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
314 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
315 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
316 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
317
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
318 int t31_t38_send_timeout(t31_state_t *s, int samples)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
319 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
320 int len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
321 uint8_t buf[100];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
322 /* Training times for all the modem options, with and without TEP */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
323 static const int training_time[] =
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
324 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
325 0, 0, /* T38_IND_NO_SIGNAL */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
326 0, 0, /* T38_IND_CNG */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
327 0, 0, /* T38_IND_CED */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
328 1000, 1000, /* T38_IND_V21_PREAMBLE */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
329 943, 1158, /* T38_IND_V27TER_2400_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
330 708, 923, /* T38_IND_V27TER_4800_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
331 234, 454, /* T38_IND_V29_7200_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
332 234, 454, /* T38_IND_V29_9600_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
333 142, 367, /* T38_IND_V17_7200_SHORT_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
334 1393, 1618, /* T38_IND_V17_7200_LONG_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
335 142, 367, /* T38_IND_V17_9600_SHORT_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
336 1393, 1618, /* T38_IND_V17_9600_LONG_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
337 142, 367, /* T38_IND_V17_12000_SHORT_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
338 1393, 1618, /* T38_IND_V17_12000_LONG_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
339 142, 367, /* T38_IND_V17_14400_SHORT_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
340 1393, 1618, /* T38_IND_V17_14400_LONG_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
341 0, 0, /* T38_IND_V8_ANSAM */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
342 0, 0, /* T38_IND_V8_SIGNAL */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
343 0, 0, /* T38_IND_V34_CNTL_CHANNEL_1200 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
344 0, 0, /* T38_IND_V34_PRI_CHANNEL */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
345 0, 0, /* T38_IND_V34_CC_RETRAIN */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
346 0, 0, /* T38_IND_V33_12000_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
347 0, 0, /* T38_IND_V33_14400_TRAINING */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
348 };
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
349
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
350 s->call_samples += samples;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
351
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
352 if (s->timed_step == T38_TIMED_STEP_NONE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
353 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
354 if (s->call_samples < s->next_send_samples)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
355 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
356 len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
357 switch (s->timed_step)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
358 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
359 case T38_TIMED_STEP_NON_ECM_MODEM:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
360 /* Create a 75ms silence */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
361 t38_core_send_indicator(&s->t38, T38_IND_NO_SIGNAL, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
362 s->timed_step = T38_TIMED_STEP_NON_ECM_MODEM_2;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
363 s->next_send_samples += ms_to_samples(75);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
364 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
365 case T38_TIMED_STEP_NON_ECM_MODEM_2:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
366 /* Switch on a fast modem, and give the training time to complete */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
367 t38_core_send_indicator(&s->t38, s->next_tx_indicator, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
368 s->timed_step = T38_TIMED_STEP_NON_ECM_MODEM_3;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
369 s->next_send_samples += ms_to_samples(training_time[s->next_tx_indicator << 1]);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
370 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
371 case T38_TIMED_STEP_NON_ECM_MODEM_3:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
372 /* Send a chunk of non-ECM image data */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
373 //if ((len = get_non_ecm_image_chunk(s, buf, s->octets_per_non_ecm_packet)))
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
374 // t38_core_send_data(&s->t38, s->current_tx_data, T38_FIELD_T4_NON_ECM_DATA, buf, abs(len));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
375 if (len > 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
376 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
377 s->next_send_samples += ms_to_samples(MS_PER_TX_CHUNK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
378 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
379 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
380 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
381 t38_core_send_data(&s->t38, s->current_tx_data, T38_FIELD_T4_NON_ECM_SIG_END, NULL, 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
382 t38_core_send_indicator(&s->t38, T38_IND_NO_SIGNAL, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
383 s->timed_step = T38_TIMED_STEP_NONE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
384 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
385 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
386 case T38_TIMED_STEP_HDLC_MODEM:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
387 /* Send HDLC preambling */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
388 t38_core_send_indicator(&s->t38, s->next_tx_indicator, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
389 s->next_send_samples += ms_to_samples(training_time[s->next_tx_indicator << 1]);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
390 s->timed_step = T38_TIMED_STEP_HDLC_MODEM_2;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
391 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
392 case T38_TIMED_STEP_HDLC_MODEM_2:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
393 /* Send HDLC octet */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
394 buf[0] = bit_reverse8(s->hdlc_tx_buf[s->hdlc_tx_ptr++]);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
395 t38_core_send_data(&s->t38, s->current_tx_data, T38_FIELD_HDLC_DATA, buf, 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
396 if (s->hdlc_tx_ptr >= s->hdlc_tx_len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
397 s->timed_step = T38_TIMED_STEP_HDLC_MODEM_3;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
398 s->next_send_samples += ms_to_samples(MS_PER_TX_CHUNK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
399 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
400 case T38_TIMED_STEP_HDLC_MODEM_3:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
401 /* End of HDLC frame */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
402 s->hdlc_tx_ptr = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
403 if (s->hdlc_final)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
404 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
405 s->hdlc_tx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
406 t38_core_send_data(&s->t38, s->current_tx_data, T38_FIELD_HDLC_FCS_OK_SIG_END, NULL, 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
407 s->timed_step = T38_TIMED_STEP_HDLC_MODEM_4;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
408 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_OK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
409 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
410 s->hdlc_final = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
411 restart_modem(s, T31_SILENCE_TX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
412 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
413 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
414 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
415 t38_core_send_data(&s->t38, s->current_tx_data, T38_FIELD_HDLC_FCS_OK, NULL, 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
416 s->timed_step = T38_TIMED_STEP_HDLC_MODEM_2;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
417 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
418 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
419 s->next_send_samples += ms_to_samples(MS_PER_TX_CHUNK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
420 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
421 case T38_TIMED_STEP_HDLC_MODEM_4:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
422 /* End of HDLC transmission */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
423 /* We have already sent T38_FIELD_HDLC_FCS_OK_SIG_END. It seems some boxes may not like
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
424 us sending a T38_FIELD_HDLC_SIG_END at this point. Just say there is no signal. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
425 //t38_core_send_data(&s->t38, s->current_tx_data, T38_FIELD_HDLC_SIG_END, NULL, 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
426 t38_core_send_indicator(&s->t38, T38_IND_NO_SIGNAL, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
427 s->timed_step = T38_TIMED_STEP_NONE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
428 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
429 case T38_TIMED_STEP_PAUSE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
430 /* End of timed pause */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
431 s->timed_step = T38_TIMED_STEP_NONE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
432 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
433 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
434 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
435 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
436 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
437
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
438 static int t31_modem_control_handler(at_state_t *s, void *user_data, int op, const char *num)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
439 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
440 t31_state_t *t;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
441
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
442 t = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
443 switch (op)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
444 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
445 case AT_MODEM_CONTROL_ANSWER:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
446 t->call_samples = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
447 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
448 case AT_MODEM_CONTROL_CALL:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
449 t->call_samples = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
450 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
451 case AT_MODEM_CONTROL_ONHOOK:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
452 if (t->tx_holding)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
453 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
454 t->tx_holding = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
455 /* Tell the application to release further data */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
456 at_modem_control(&t->at_state, AT_MODEM_CONTROL_CTS, (void *) 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
457 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
458 if (t->at_state.rx_signal_present)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
459 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
460 t->at_state.rx_data[t->at_state.rx_data_bytes++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
461 t->at_state.rx_data[t->at_state.rx_data_bytes++] = ETX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
462 t->at_state.at_tx_handler(&t->at_state, t->at_state.at_tx_user_data, t->at_state.rx_data, t->at_state.rx_data_bytes);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
463 t->at_state.rx_data_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
464 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
465 restart_modem(t, T31_SILENCE_TX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
466 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
467 case AT_MODEM_CONTROL_RESTART:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
468 restart_modem(t, (int) (intptr_t) num);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
469 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
470 case AT_MODEM_CONTROL_DTE_TIMEOUT:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
471 if (num)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
472 t->dte_data_timeout = t->call_samples + ms_to_samples((intptr_t) num);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
473 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
474 t->dte_data_timeout = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
475 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
476 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
477 return t->modem_control_handler(t, t->modem_control_user_data, op, num);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
478 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
479 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
480
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
481 static void non_ecm_put_bit(void *user_data, int bit)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
482 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
483 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
484
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
485 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
486 if (bit < 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
487 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
488 /* Special conditions */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
489 switch (bit)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
490 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
491 case PUTBIT_TRAINING_FAILED:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
492 s->at_state.rx_trained = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
493 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
494 case PUTBIT_TRAINING_SUCCEEDED:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
495 /* The modem is now trained */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
496 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
497 s->at_state.rx_signal_present = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
498 s->at_state.rx_trained = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
499 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
500 case PUTBIT_CARRIER_UP:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
501 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
502 case PUTBIT_CARRIER_DOWN:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
503 if (s->at_state.rx_signal_present)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
504 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
505 s->at_state.rx_data[s->at_state.rx_data_bytes++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
506 s->at_state.rx_data[s->at_state.rx_data_bytes++] = ETX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
507 s->at_state.at_tx_handler(&s->at_state, s->at_state.at_tx_user_data, s->at_state.rx_data, s->at_state.rx_data_bytes);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
508 s->at_state.rx_data_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
509 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_NO_CARRIER);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
510 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
511 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
512 s->at_state.rx_signal_present = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
513 s->at_state.rx_trained = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
514 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
515 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
516 if (s->at_state.p.result_code_format)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
517 span_log(&s->logging, SPAN_LOG_FLOW, "Eh!\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
518 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
519 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
520 return;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
521 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
522 s->current_byte = (s->current_byte >> 1) | (bit << 7);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
523 if (++s->bit_no >= 8)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
524 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
525 if (s->current_byte == DLE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
526 s->at_state.rx_data[s->at_state.rx_data_bytes++] = (uint8_t) s->current_byte;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
527 s->at_state.rx_data[s->at_state.rx_data_bytes++] = (uint8_t) s->current_byte;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
528 if (s->at_state.rx_data_bytes >= 250)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
529 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
530 s->at_state.at_tx_handler(&s->at_state, s->at_state.at_tx_user_data, s->at_state.rx_data, s->at_state.rx_data_bytes);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
531 s->at_state.rx_data_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
532 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
533 s->bit_no = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
534 s->current_byte = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
535 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
536 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
537 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
538
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
539 static int non_ecm_get_bit(void *user_data)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
540 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
541 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
542 int bit;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
543 int fill;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
544
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
545 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
546 if (s->bit_no <= 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
547 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
548 if (s->tx_out_bytes != s->tx_in_bytes)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
549 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
550 /* There is real data available to send */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
551 s->current_byte = s->tx_data[s->tx_out_bytes];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
552 s->tx_out_bytes = (s->tx_out_bytes + 1) & (T31_TX_BUF_LEN - 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
553 if (s->tx_holding)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
554 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
555 /* See if the buffer is approaching empty. It might be time to release flow control. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
556 fill = (s->tx_in_bytes - s->tx_out_bytes);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
557 if (s->tx_in_bytes < s->tx_out_bytes)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
558 fill += (T31_TX_BUF_LEN + 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
559 if (fill < T31_TX_BUF_LOW_TIDE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
560 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
561 s->tx_holding = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
562 /* Tell the application to release further data */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
563 at_modem_control(&s->at_state, AT_MODEM_CONTROL_CTS, (void *) 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
564 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
565 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
566 s->tx_data_started = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
567 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
568 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
569 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
570 if (s->data_final)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
571 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
572 s->data_final = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
573 /* This will put the modem into its shutdown sequence. When
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
574 it has finally shut down, an OK response will be sent. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
575 return PUTBIT_END_OF_DATA;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
576 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
577 /* Fill with 0xFF bytes at the start of transmission, or 0x00 if we are in
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
578 the middle of transmission. This follows T.31 and T.30 practice. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
579 s->current_byte = (s->tx_data_started) ? 0x00 : 0xFF;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
580 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
581 s->bit_no = 8;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
582 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
583 s->bit_no--;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
584 bit = s->current_byte & 1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
585 s->current_byte >>= 1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
586 return bit;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
587 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
588 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
589
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
590 static void hdlc_tx_underflow(void *user_data)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
591 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
592 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
593
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
594 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
595 if (s->hdlc_final)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
596 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
597 s->hdlc_final = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
598 /* Schedule an orderly shutdown of the modem */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
599 hdlc_tx_frame(&(s->hdlctx), NULL, 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
600 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
601 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
602 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
603 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
604 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
605 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
606 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
607
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
608 static void hdlc_accept(void *user_data, int ok, const uint8_t *msg, int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
609 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
610 uint8_t buf[256];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
611 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
612 int i;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
613
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
614 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
615 if (len < 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
616 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
617 /* Special conditions */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
618 switch (len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
619 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
620 case PUTBIT_TRAINING_FAILED:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
621 s->at_state.rx_trained = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
622 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
623 case PUTBIT_TRAINING_SUCCEEDED:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
624 /* The modem is now trained */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
625 s->at_state.rx_signal_present = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
626 s->at_state.rx_trained = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
627 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
628 case PUTBIT_CARRIER_UP:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
629 if (s->modem == T31_CNG_TONE || s->modem == T31_NOCNG_TONE || s->modem == T31_V21_RX)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
630 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
631 s->at_state.rx_signal_present = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
632 s->rx_message_received = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
633 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
634 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
635 case PUTBIT_CARRIER_DOWN:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
636 if (s->rx_message_received)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
637 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
638 if (s->at_state.dte_is_waiting)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
639 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
640 if (s->at_state.ok_is_pending)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
641 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
642 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_OK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
643 s->at_state.ok_is_pending = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
644 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
645 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
646 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
647 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_NO_CARRIER);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
648 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
649 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
650 s->at_state.dte_is_waiting = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
651 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
652 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
653 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
654 buf[0] = AT_RESPONSE_CODE_NO_CARRIER;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
655 queue_write_msg(&(s->rx_queue), buf, 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
656 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
657 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
658 s->at_state.rx_signal_present = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
659 s->at_state.rx_trained = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
660 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
661 case PUTBIT_FRAMING_OK:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
662 if (s->modem == T31_CNG_TONE || s->modem == T31_NOCNG_TONE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
663 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
664 /* Once we get any valid HDLC the CNG tone stops, and we drop
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
665 to the V.21 receive modem on its own. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
666 s->modem = T31_V21_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
667 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
668 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
669 if (s->modem != T31_V21_RX)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
670 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
671 /* V.21 has been detected while expecting a different carrier.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
672 If +FAR=0 then result +FCERROR and return to command-mode.
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
673 If +FAR=1 then report +FRH:3 and CONNECT, switching to
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
674 V.21 receive mode. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
675 if (s->at_state.p.adaptive_receive)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
676 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
677 s->at_state.rx_signal_present = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
678 s->rx_message_received = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
679 s->modem = T31_V21_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
680 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
681 s->at_state.dte_is_waiting = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
682 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_FRH3);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
683 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
684 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
685 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
686 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
687 s->modem = T31_SILENCE_TX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
688 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
689 s->rx_message_received = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
690 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_FCERROR);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
691 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
692 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
693 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
694 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
695 if (!s->rx_message_received)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
696 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
697 /* Report CONNECT as soon as possible to avoid a timeout. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
698 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
699 s->rx_message_received = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
700 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
701 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
702 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
703 case PUTBIT_ABORT:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
704 /* Just ignore these */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
705 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
706 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
707 span_log(&s->logging, SPAN_LOG_WARNING, "Unexpected HDLC special length - %d!\n", len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
708 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
709 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
710 return;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
711 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
712 /* If OK is pending then we just ignore whatever comes in */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
713 if (!s->at_state.ok_is_pending)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
714 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
715 if (s->at_state.dte_is_waiting)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
716 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
717 /* Send straight away */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
718 /* It is safe to look at the two bytes beyond the length of the message,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
719 and expect to find the FCS there. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
720 for (i = 0; i < len + 2; i++)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
721 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
722 if (msg[i] == DLE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
723 s->at_state.rx_data[s->at_state.rx_data_bytes++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
724 s->at_state.rx_data[s->at_state.rx_data_bytes++] = msg[i];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
725 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
726 s->at_state.rx_data[s->at_state.rx_data_bytes++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
727 s->at_state.rx_data[s->at_state.rx_data_bytes++] = ETX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
728 s->at_state.at_tx_handler(&s->at_state, s->at_state.at_tx_user_data, s->at_state.rx_data, s->at_state.rx_data_bytes);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
729 s->at_state.rx_data_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
730 if (msg[1] == 0x13 && ok)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
731 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
732 /* This is the last frame. We don't send OK until the carrier drops to avoid
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
733 redetecting it later. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
734 s->at_state.ok_is_pending = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
735 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
736 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
737 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
738 at_put_response_code(&s->at_state, (ok) ? AT_RESPONSE_CODE_OK : AT_RESPONSE_CODE_ERROR);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
739 s->at_state.dte_is_waiting = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
740 s->rx_message_received = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
741 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
742 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
743 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
744 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
745 /* Queue it */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
746 buf[0] = (ok) ? AT_RESPONSE_CODE_OK : AT_RESPONSE_CODE_ERROR;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
747 /* It is safe to look at the two bytes beyond the length of the message,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
748 and expect to find the FCS there. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
749 memcpy(buf + 1, msg, len + 2);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
750 queue_write_msg(&(s->rx_queue), buf, len + 3);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
751 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
752 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
753 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
754 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
755 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
756
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
757 static void t31_v21_rx(t31_state_t *s)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
758 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
759 hdlc_rx_init(&(s->hdlcrx), FALSE, TRUE, 5, hdlc_accept, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
760 s->at_state.ok_is_pending = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
761 s->hdlc_final = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
762 s->hdlc_tx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
763 s->dled = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
764 fsk_rx_init(&(s->v21rx), &preset_fsk_specs[FSK_V21CH2], TRUE, (put_bit_func_t) hdlc_rx_put_bit, &(s->hdlcrx));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
765 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
766 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
767 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
768
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
769 static int restart_modem(t31_state_t *s, int new_modem)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
770 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
771 tone_gen_descriptor_t tone_desc;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
772 int ind;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
773
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
774 span_log(&s->logging, SPAN_LOG_FLOW, "Restart modem %d\n", new_modem);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
775 if (s->modem == new_modem)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
776 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
777 queue_flush(&(s->rx_queue));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
778 s->modem = new_modem;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
779 s->data_final = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
780 s->at_state.rx_signal_present = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
781 s->at_state.rx_trained = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
782 s->rx_message_received = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
783 s->rx_handler = (span_rx_handler_t *) &dummy_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
784 s->rx_user_data = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
785 switch (s->modem)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
786 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
787 case T31_CNG_TONE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
788 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
789 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
790 t38_core_send_indicator(&s->t38, T38_IND_CNG, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
791 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
792 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
793 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
794 /* CNG is special, since we need to receive V.21 HDLC messages while sending the
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
795 tone. Everything else in FAX processing sends only one way at a time. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
796 /* 0.5s of 1100Hz + 3.0s of silence repeating */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
797 make_tone_gen_descriptor(&tone_desc,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
798 1100,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
799 -11,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
800 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
801 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
802 500,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
803 3000,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
804 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
805 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
806 TRUE);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
807 tone_gen_init(&(s->tone_gen), &tone_desc);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
808 /* Do V.21/HDLC receive in parallel. The other end may send its
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
809 first message at any time. The CNG tone will continue until
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
810 we get a valid preamble. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
811 s->rx_handler = (span_rx_handler_t *) &cng_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
812 s->rx_user_data = s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
813 t31_v21_rx(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
814 s->tx_handler = (span_tx_handler_t *) &tone_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
815 s->tx_user_data = &(s->tone_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
816 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
817 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
818 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
819 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
820 case T31_NOCNG_TONE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
821 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
822 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
823 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
824 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
825 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
826 s->rx_handler = (span_rx_handler_t *) &cng_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
827 s->rx_user_data = s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
828 t31_v21_rx(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
829 silence_gen_set(&(s->silence_gen), 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
830 s->tx_handler = (span_tx_handler_t *) &silence_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
831 s->tx_user_data = &(s->silence_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
832 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
833 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
834 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
835 case T31_CED_TONE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
836 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
837 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
838 t38_core_send_indicator(&s->t38, T38_IND_CED, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
839 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
840 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
841 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
842 silence_gen_alter(&(s->silence_gen), ms_to_samples(200));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
843 make_tone_gen_descriptor(&tone_desc,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
844 2100,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
845 -11,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
846 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
847 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
848 2600,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
849 75,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
850 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
851 0,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
852 FALSE);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
853 tone_gen_init(&(s->tone_gen), &tone_desc);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
854 s->tx_handler = (span_tx_handler_t *) &silence_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
855 s->tx_user_data = &(s->silence_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
856 s->next_tx_handler = (span_tx_handler_t *) &tone_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
857 s->next_tx_user_data = &(s->tone_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
858 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
859 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
860 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
861 case T31_V21_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
862 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
863 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
864 t38_core_send_indicator(&s->t38, T38_IND_V21_PREAMBLE, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
865 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
866 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
867 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
868 hdlc_tx_init(&(s->hdlctx), FALSE, 2, FALSE, hdlc_tx_underflow, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
869 /* The spec says 1s +-15% of preamble. So, the minimum is 32 octets. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
870 hdlc_tx_preamble(&(s->hdlctx), 32);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
871 fsk_tx_init(&(s->v21tx), &preset_fsk_specs[FSK_V21CH2], (get_bit_func_t) hdlc_tx_get_bit, &(s->hdlctx));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
872 s->tx_handler = (span_tx_handler_t *) &fsk_tx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
873 s->tx_user_data = &(s->v21tx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
874 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
875 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
876 s->hdlc_final = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
877 s->hdlc_tx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
878 s->dled = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
879 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
880 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
881 case T31_V21_RX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
882 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
883 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
884 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
885 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
886 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
887 s->rx_handler = (span_rx_handler_t *) &fsk_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
888 s->rx_user_data = &(s->v21rx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
889 t31_v21_rx(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
890 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
891 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
892 #if defined(ENABLE_V17)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
893 case T31_V17_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
894 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
895 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
896 switch (s->bit_rate)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
897 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
898 case 7200:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
899 ind = (s->short_train) ? T38_IND_V17_7200_SHORT_TRAINING : T38_IND_V17_7200_LONG_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
900 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
901 case 9600:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
902 ind = (s->short_train) ? T38_IND_V17_9600_SHORT_TRAINING : T38_IND_V17_9600_LONG_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
903 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
904 case 12000:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
905 ind = (s->short_train) ? T38_IND_V17_12000_SHORT_TRAINING : T38_IND_V17_12000_LONG_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
906 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
907 case 14400:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
908 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
909 ind = (s->short_train) ? T38_IND_V17_14400_SHORT_TRAINING : T38_IND_V17_14400_LONG_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
910 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
911 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
912 t38_core_send_indicator(&s->t38, ind, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
913 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
914 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
915 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
916 v17_tx_restart(&(s->v17tx), s->bit_rate, FALSE, s->short_train);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
917 s->tx_handler = (span_tx_handler_t *) &v17_tx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
918 s->tx_user_data = &(s->v17tx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
919 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
920 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
921 s->tx_out_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
922 s->tx_data_started = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
923 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
924 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
925 case T31_V17_RX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
926 if (!s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
927 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
928 s->rx_handler = (span_rx_handler_t *) &early_v17_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
929 s->rx_user_data = s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
930 v17_rx_restart(&(s->v17rx), s->bit_rate, s->short_train);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
931 /* Allow for +FCERROR/+FRH:3 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
932 t31_v21_rx(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
933 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
934 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
935 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
936 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
937 case T31_V27TER_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
938 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
939 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
940 switch (s->bit_rate)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
941 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
942 case 2400:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
943 ind = T38_IND_V27TER_2400_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
944 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
945 case 4800:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
946 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
947 ind = T38_IND_V27TER_4800_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
948 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
949 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
950 t38_core_send_indicator(&s->t38, ind, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
951 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
952 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
953 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
954 v27ter_tx_restart(&(s->v27ter_tx), s->bit_rate, FALSE);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
955 s->tx_handler = (span_tx_handler_t *) &v27ter_tx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
956 s->tx_user_data = &(s->v27ter_tx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
957 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
958 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
959 s->tx_out_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
960 s->tx_data_started = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
961 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
962 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
963 case T31_V27TER_RX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
964 if (!s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
965 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
966 s->rx_handler = (span_rx_handler_t *) &early_v27ter_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
967 s->rx_user_data = s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
968 v27ter_rx_restart(&(s->v27ter_rx), s->bit_rate, FALSE);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
969 /* Allow for +FCERROR/+FRH:3 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
970 t31_v21_rx(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
971 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
972 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
973 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
974 case T31_V29_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
975 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
976 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
977 switch (s->bit_rate)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
978 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
979 case 7200:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
980 ind = T38_IND_V29_7200_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
981 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
982 case 9600:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
983 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
984 ind = T38_IND_V29_9600_TRAINING;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
985 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
986 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
987 t38_core_send_indicator(&s->t38, ind, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
988 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
989 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
990 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
991 v29_tx_restart(&(s->v29tx), s->bit_rate, FALSE);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
992 s->tx_handler = (span_tx_handler_t *) &v29_tx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
993 s->tx_user_data = &(s->v29tx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
994 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
995 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
996 s->tx_out_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
997 s->tx_data_started = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
998 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
999 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1000 case T31_V29_RX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1001 if (!s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1002 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1003 s->rx_handler = (span_rx_handler_t *) &early_v29_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1004 s->rx_user_data = s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1005 v29_rx_restart(&(s->v29rx), s->bit_rate, FALSE);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1006 /* Allow for +FCERROR/+FRH:3 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1007 t31_v21_rx(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1008 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1009 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1010 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1011 case T31_SILENCE_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1012 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1013 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1014 t38_core_send_indicator(&s->t38, T38_IND_NO_SIGNAL, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1015 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1016 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1017 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1018 silence_gen_set(&(s->silence_gen), 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1019 s->tx_handler = (span_tx_handler_t *) &silence_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1020 s->tx_user_data = &(s->silence_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1021 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1022 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1023 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1024 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1025 case T31_SILENCE_RX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1026 if (!s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1027 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1028 s->rx_handler = (span_rx_handler_t *) &silence_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1029 s->rx_user_data = s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1030
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1031 silence_gen_set(&(s->silence_gen), 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1032 s->tx_handler = (span_tx_handler_t *) &silence_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1033 s->tx_user_data = &(s->silence_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1034 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1035 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1036 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1037 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1038 case T31_FLUSH:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1039 /* Send 200ms of silence to "push" the last audio out */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1040 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1041 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1042 t38_core_send_indicator(&s->t38, T38_IND_NO_SIGNAL, INDICATOR_TX_COUNT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1043 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1044 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1045 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1046 s->modem = T31_SILENCE_TX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1047 silence_gen_alter(&(s->silence_gen), ms_to_samples(200));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1048 s->tx_handler = (span_tx_handler_t *) &silence_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1049 s->tx_user_data = &(s->silence_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1050 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1051 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1052 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1053 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1054 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1055 s->bit_no = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1056 s->current_byte = 0xFF;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1057 s->tx_in_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1058 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1059 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1060 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1061
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1062 static __inline__ void dle_unstuff_hdlc(t31_state_t *s, const char *stuffed, int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1063 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1064 int i;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1065
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1066 for (i = 0; i < len; i++)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1067 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1068 if (s->dled)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1069 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1070 s->dled = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1071 if (stuffed[i] == ETX)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1072 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1073 if (s->t38_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1074 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1075 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1076 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1077 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1078 hdlc_tx_frame(&(s->hdlctx), s->hdlc_tx_buf, s->hdlc_tx_len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1079 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1080 s->hdlc_final = (s->hdlc_tx_buf[1] & 0x10);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1081 s->hdlc_tx_len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1082 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1083 else if (stuffed[i] == SUB)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1084 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1085 s->hdlc_tx_buf[s->hdlc_tx_len++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1086 s->hdlc_tx_buf[s->hdlc_tx_len++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1087 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1088 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1089 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1090 s->hdlc_tx_buf[s->hdlc_tx_len++] = stuffed[i];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1091 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1092 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1093 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1094 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1095 if (stuffed[i] == DLE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1096 s->dled = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1097 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1098 s->hdlc_tx_buf[s->hdlc_tx_len++] = stuffed[i];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1099 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1100 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1101 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1102 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1103
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1104 static __inline__ void dle_unstuff(t31_state_t *s, const char *stuffed, int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1105 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1106 int i;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1107 int fill;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1108 int next;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1109
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1110 for (i = 0; i < len; i++)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1111 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1112 if (s->dled)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1113 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1114 s->dled = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1115 if (stuffed[i] == ETX)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1116 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1117 s->data_final = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1118 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1119 return;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1120 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1121 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1122 else if (stuffed[i] == DLE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1123 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1124 s->dled = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1125 continue;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1126 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1127 s->tx_data[s->tx_in_bytes] = stuffed[i];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1128 next = (s->tx_in_bytes + 1) & (T31_TX_BUF_LEN - 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1129 if (next == s->tx_out_bytes)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1130 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1131 /* Oops. We hit the end of the buffer. Give up. Loose stuff. :-( */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1132 return;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1133 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1134 s->tx_in_bytes = next;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1135 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1136 if (!s->tx_holding)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1137 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1138 /* See if the buffer is approaching full. We might need to apply flow control. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1139 fill = (s->tx_in_bytes - s->tx_out_bytes);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1140 if (s->tx_in_bytes < s->tx_out_bytes)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1141 fill += (T31_TX_BUF_LEN + 1);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1142 if (fill > T31_TX_BUF_HIGH_TIDE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1143 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1144 s->tx_holding = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1145 /* Tell the application to hold further data */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1146 at_modem_control(&s->at_state, AT_MODEM_CONTROL_CTS, (void *) 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1147 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1148 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1149 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1150 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1151
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1152 static int process_class1_cmd(at_state_t *t, void *user_data, int direction, int operation, int val)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1153 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1154 int new_modem;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1155 int new_transmit;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1156 int i;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1157 int len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1158 int immediate_response;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1159 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1160 uint8_t msg[256];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1161
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1162 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1163 new_transmit = direction;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1164 immediate_response = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1165 switch (operation)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1166 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1167 case 'S':
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1168 s->at_state.transmit = new_transmit;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1169 if (new_transmit)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1170 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1171 /* Send a specified period of silence, to space transmissions. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1172 restart_modem(s, T31_SILENCE_TX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1173 silence_gen_alter(&(s->silence_gen), val*80);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1174 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1175 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1176 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1177 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1178 /* Wait until we have received a specified period of silence. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1179 queue_flush(&(s->rx_queue));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1180 s->silence_awaited = val*80;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1181 t31_set_at_rx_mode(s, AT_MODE_DELIVERY);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1182 restart_modem(s, T31_SILENCE_RX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1183 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1184 immediate_response = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1185 span_log(&s->logging, SPAN_LOG_FLOW, "Silence %dms\n", val*10);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1186 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1187 case 'H':
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1188 switch (val)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1189 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1190 case 3:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1191 new_modem = (new_transmit) ? T31_V21_TX : T31_V21_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1192 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1193 s->bit_rate = 300;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1194 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1195 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1196 return -1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1197 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1198 span_log(&s->logging, SPAN_LOG_FLOW, "HDLC\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1199 if (new_modem != s->modem)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1200 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1201 restart_modem(s, new_modem);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1202 immediate_response = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1203 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1204 s->at_state.transmit = new_transmit;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1205 if (new_transmit)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1206 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1207 t31_set_at_rx_mode(s, AT_MODE_HDLC);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1208 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1209 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1210 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1211 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1212 /* Send straight away, if there is something queued. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1213 t31_set_at_rx_mode(s, AT_MODE_DELIVERY);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1214 s->rx_message_received = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1215 do
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1216 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1217 if (!queue_empty(&(s->rx_queue)))
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1218 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1219 len = queue_read_msg(&(s->rx_queue), msg, 256);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1220 if (len > 1)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1221 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1222 if (msg[0] == AT_RESPONSE_CODE_OK)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1223 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1224 for (i = 1; i < len; i++)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1225 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1226 if (msg[i] == DLE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1227 s->at_state.rx_data[s->at_state.rx_data_bytes++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1228 s->at_state.rx_data[s->at_state.rx_data_bytes++] = msg[i];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1229 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1230 s->at_state.rx_data[s->at_state.rx_data_bytes++] = DLE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1231 s->at_state.rx_data[s->at_state.rx_data_bytes++] = ETX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1232 s->at_state.at_tx_handler(&s->at_state, s->at_state.at_tx_user_data, s->at_state.rx_data, s->at_state.rx_data_bytes);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1233 s->at_state.rx_data_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1234 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1235 at_put_response_code(&s->at_state, msg[0]);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1236 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1237 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1238 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1239 s->at_state.dte_is_waiting = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1240 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1241 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1242 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1243 while (msg[0] == AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1244 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1245 immediate_response = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1246 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1247 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1248 switch (val)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1249 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1250 case 24:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1251 new_modem = (new_transmit) ? T31_V27TER_TX : T31_V27TER_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1252 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1253 s->bit_rate = 2400;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1254 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1255 case 48:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1256 new_modem = (new_transmit) ? T31_V27TER_TX : T31_V27TER_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1257 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1258 s->bit_rate = 4800;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1259 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1260 case 72:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1261 new_modem = (new_transmit) ? T31_V29_TX : T31_V29_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1262 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1263 s->bit_rate = 7200;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1264 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1265 case 96:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1266 new_modem = (new_transmit) ? T31_V29_TX : T31_V29_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1267 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1268 s->bit_rate = 9600;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1269 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1270 #if defined(ENABLE_V17)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1271 case 73:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1272 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1273 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1274 s->bit_rate = 7200;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1275 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1276 case 74:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1277 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1278 s->short_train = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1279 s->bit_rate = 7200;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1280 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1281 case 97:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1282 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1283 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1284 s->bit_rate = 9600;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1285 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1286 case 98:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1287 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1288 s->short_train = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1289 s->bit_rate = 9600;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1290 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1291 case 121:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1292 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1293 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1294 s->bit_rate = 12000;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1295 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1296 case 122:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1297 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1298 s->short_train = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1299 s->bit_rate = 12000;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1300 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1301 case 145:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1302 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1303 s->short_train = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1304 s->bit_rate = 14400;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1305 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1306 case 146:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1307 new_modem = (new_transmit) ? T31_V17_TX : T31_V17_RX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1308 s->short_train = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1309 s->bit_rate = 14400;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1310 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1311 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1312 default:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1313 return -1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1314 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1315 span_log(&s->logging, SPAN_LOG_FLOW, "Short training = %d, bit rate = %d\n", s->short_train, s->bit_rate);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1316 if (new_transmit)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1317 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1318 t31_set_at_rx_mode(s, AT_MODE_STUFFED);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1319 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_CONNECT);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1320 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1321 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1322 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1323 t31_set_at_rx_mode(s, AT_MODE_DELIVERY);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1324 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1325 restart_modem(s, new_modem);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1326 immediate_response = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1327 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1328 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1329 return immediate_response;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1330 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1331 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1332
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1333 void t31_call_event(t31_state_t *s, int event)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1334 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1335 span_log(&s->logging, SPAN_LOG_FLOW, "Call event %d received\n", event);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1336 at_call_event(&s->at_state, event);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1337 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1338 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1339
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1340 int t31_at_rx(t31_state_t *s, const char *t, int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1341 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1342 if (s->dte_data_timeout)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1343 s->dte_data_timeout = s->call_samples + ms_to_samples(5000);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1344 switch (s->at_state.at_rx_mode)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1345 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1346 case AT_MODE_ONHOOK_COMMAND:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1347 case AT_MODE_OFFHOOK_COMMAND:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1348 at_interpreter(&s->at_state, t, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1349 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1350 case AT_MODE_DELIVERY:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1351 /* Data from the DTE in this state returns us to command mode */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1352 if (len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1353 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1354 s->at_state.rx_data_bytes = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1355 s->at_state.transmit = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1356 s->modem = T31_SILENCE_TX;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1357 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1358 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_OK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1359 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1360 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1361 case AT_MODE_HDLC:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1362 dle_unstuff_hdlc(s, t, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1363 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1364 case AT_MODE_STUFFED:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1365 dle_unstuff(s, t, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1366 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1367 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1368 return len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1369 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1370 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1371
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1372 static int dummy_rx(void *user_data, const int16_t amp[], int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1373 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1374 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1375 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1376 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1377
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1378 static int silence_rx(void *user_data, const int16_t amp[], int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1379 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1380 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1381
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1382 /* Searching for a specified minimum period of silence. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1383 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1384 if (s->silence_awaited && s->silence_heard >= s->silence_awaited)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1385 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1386 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_OK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1387 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1388 s->silence_heard = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1389 s->silence_awaited = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1390 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1391 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1392 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1393 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1394
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1395 static int cng_rx(void *user_data, const int16_t amp[], int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1396 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1397 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1398
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1399 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1400 if (s->call_samples > ms_to_samples(s->at_state.p.s_regs[7]*1000))
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1401 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1402 /* After calling, S7 has elapsed... no carrier found. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1403 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_NO_CARRIER);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1404 restart_modem(s, T31_SILENCE_TX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1405 at_modem_control(&s->at_state, AT_MODEM_CONTROL_HANGUP, NULL);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1406 t31_set_at_rx_mode(s, AT_MODE_ONHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1407 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1408 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1409 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1410 fsk_rx(&(s->v21rx), amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1411 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1412 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1413 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1414 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1415
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1416 #if defined(ENABLE_V17)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1417 static int early_v17_rx(void *user_data, const int16_t amp[], int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1418 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1419 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1420
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1421 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1422 v17_rx(&(s->v17rx), amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1423 if (s->at_state.rx_trained)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1424 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1425 /* The fast modem has trained, so we no longer need to run the slow
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1426 one in parallel. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1427 span_log(&s->logging, SPAN_LOG_FLOW, "Switching from V.17 + V.21 to V.17 (%.2fdBm0)\n", v17_rx_signal_power(&(s->v17rx)));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1428 s->rx_handler = (span_rx_handler_t *) &v17_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1429 s->rx_user_data = &(s->v17rx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1430 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1431 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1432 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1433 fsk_rx(&(s->v21rx), amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1434 if (s->rx_message_received)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1435 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1436 /* We have received something, and the fast modem has not trained. We must
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1437 be receiving valid V.21 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1438 span_log(&s->logging, SPAN_LOG_FLOW, "Switching from V.17 + V.21 to V.21\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1439 s->rx_handler = (span_rx_handler_t *) &fsk_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1440 s->rx_user_data = &(s->v21rx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1441 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1442 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1443 return len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1444 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1445 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1446 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1447
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1448 static int early_v27ter_rx(void *user_data, const int16_t amp[], int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1449 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1450 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1451
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1452 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1453 v27ter_rx(&(s->v27ter_rx), amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1454 if (s->at_state.rx_trained)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1455 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1456 /* The fast modem has trained, so we no longer need to run the slow
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1457 one in parallel. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1458 span_log(&s->logging, SPAN_LOG_FLOW, "Switching from V.27ter + V.21 to V.27ter (%.2fdBm0)\n", v27ter_rx_signal_power(&(s->v27ter_rx)));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1459 s->rx_handler = (span_rx_handler_t *) &v27ter_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1460 s->rx_user_data = &(s->v27ter_rx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1461 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1462 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1463 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1464 fsk_rx(&(s->v21rx), amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1465 if (s->rx_message_received)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1466 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1467 /* We have received something, and the fast modem has not trained. We must
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1468 be receiving valid V.21 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1469 span_log(&s->logging, SPAN_LOG_FLOW, "Switching from V.27ter + V.21 to V.21\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1470 s->rx_handler = (span_rx_handler_t *) &fsk_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1471 s->rx_user_data = &(s->v21rx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1472 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1473 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1474 return len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1475 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1476 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1477
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1478 static int early_v29_rx(void *user_data, const int16_t amp[], int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1479 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1480 t31_state_t *s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1481
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1482 s = (t31_state_t *) user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1483 v29_rx(&(s->v29rx), amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1484 if (s->at_state.rx_trained)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1485 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1486 /* The fast modem has trained, so we no longer need to run the slow
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1487 one in parallel. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1488 span_log(&s->logging, SPAN_LOG_FLOW, "Switching from V.29 + V.21 to V.29 (%.2fdBm0)\n", v29_rx_signal_power(&(s->v29rx)));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1489 s->rx_handler = (span_rx_handler_t *) &v29_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1490 s->rx_user_data = &(s->v29rx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1491 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1492 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1493 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1494 fsk_rx(&(s->v21rx), amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1495 if (s->rx_message_received)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1496 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1497 /* We have received something, and the fast modem has not trained. We must
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1498 be receiving valid V.21 */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1499 span_log(&s->logging, SPAN_LOG_FLOW, "Switching from V.29 + V.21 to V.21\n");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1500 s->rx_handler = (span_rx_handler_t *) &fsk_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1501 s->rx_user_data = &(s->v21rx);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1502 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1503 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1504 return len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1505 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1506 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1507
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1508 int t31_rx(t31_state_t *s, int16_t amp[], int len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1509 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1510 int i;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1511 int32_t power;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1512
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1513 /* Monitor for received silence. Maximum needed detection is AT+FRS=255 (255*10ms). */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1514 /* We could probably only run this loop if (s->modem == T31_SILENCE_RX), however,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1515 the spec says "when silence has been present on the line for the amount of
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1516 time specified". That means some of the silence may have occurred before
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1517 the AT+FRS=n command. This condition, however, is not likely to ever be the
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1518 case. (AT+FRS=n will usually be issued before the remote goes silent.) */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1519 for (i = 0; i < len; i++)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1520 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1521 /* Clean up any DC influence. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1522 power = power_meter_update(&(s->rx_power), amp[i] - s->last_sample);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1523 s->last_sample = amp[i];
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1524 if (power > s->silence_threshold_power)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1525 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1526 s->silence_heard = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1527 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1528 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1529 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1530 if (s->silence_heard <= ms_to_samples(255*10))
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1531 s->silence_heard++;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1532 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1533 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1534
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1535 /* Time is determined by counting the samples in audio packets coming in. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1536 s->call_samples += len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1537
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1538 /* In HDLC transmit mode, if 5 seconds elapse without data from the DTE
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1539 we must treat this as an error. We return the result ERROR, and change
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1540 to command-mode. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1541 if (s->dte_data_timeout && s->call_samples > s->dte_data_timeout)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1542 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1543 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1544 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_ERROR);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1545 restart_modem(s, T31_SILENCE_TX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1546 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1547
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1548 if (!s->at_state.transmit || s->modem == T31_CNG_TONE)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1549 s->rx_handler(s->rx_user_data, amp, len);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1550 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1551 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1552 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1553
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1554 static int set_next_tx_type(t31_state_t *s)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1555 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1556 if (s->next_tx_handler)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1557 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1558 s->tx_handler = s->next_tx_handler;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1559 s->tx_user_data = s->next_tx_user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1560 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1561 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1562 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1563 /* If there is nothing else to change to, so use zero length silence */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1564 silence_gen_alter(&(s->silence_gen), 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1565 s->tx_handler = (span_tx_handler_t *) &silence_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1566 s->tx_user_data = &(s->silence_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1567 s->next_tx_handler = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1568 return -1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1569 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1570 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1571
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1572 int t31_tx(t31_state_t *s, int16_t amp[], int max_len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1573 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1574 int len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1575
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1576 len = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1577 if (s->at_state.transmit)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1578 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1579 if ((len = s->tx_handler(s->tx_user_data, amp, max_len)) < max_len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1580 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1581 /* Allow for one change of tx handler within a block */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1582 set_next_tx_type(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1583 if ((len += s->tx_handler(s->tx_user_data, amp + len, max_len - len)) < max_len)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1584 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1585 switch (s->modem)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1586 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1587 case T31_SILENCE_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1588 s->modem = -1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1589 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_OK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1590 if (s->at_state.do_hangup)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1591 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1592 at_modem_control(&s->at_state, AT_MODEM_CONTROL_HANGUP, NULL);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1593 t31_set_at_rx_mode(s, AT_MODE_ONHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1594 s->at_state.do_hangup = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1595 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1596 else
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1597 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1598 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1599 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1600 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1601 case T31_CED_TONE:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1602 /* Go directly to V.21/HDLC transmit. */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1603 s->modem = -1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1604 restart_modem(s, T31_V21_TX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1605 t31_set_at_rx_mode(s, AT_MODE_HDLC);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1606 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1607 case T31_V21_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1608 #if defined(ENABLE_V17)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1609 case T31_V17_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1610 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1611 case T31_V27TER_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1612 case T31_V29_TX:
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1613 s->modem = -1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1614 at_put_response_code(&s->at_state, AT_RESPONSE_CODE_OK);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1615 t31_set_at_rx_mode(s, AT_MODE_OFFHOOK_COMMAND);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1616 restart_modem(s, T31_SILENCE_TX);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1617 break;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1618 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1619 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1620 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1621 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1622 if (s->transmit_on_idle)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1623 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1624 /* Pad to the requested length with silence */
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1625 memset(amp, 0, max_len*sizeof(int16_t));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1626 len = max_len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1627 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1628 return len;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1629 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1630 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1631
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1632 void t31_set_transmit_on_idle(t31_state_t *s, int transmit_on_idle)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1633 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1634 s->transmit_on_idle = transmit_on_idle;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1635 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1636 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1637
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1638 t31_state_t *t31_init(t31_state_t *s,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1639 at_tx_handler_t *at_tx_handler,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1640 void *at_tx_user_data,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1641 t31_modem_control_handler_t *modem_control_handler,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1642 void *modem_control_user_data,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1643 t38_tx_packet_handler_t *tx_t38_packet_handler,
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1644 void *tx_t38_packet_user_data)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1645 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1646 if (at_tx_handler == NULL || modem_control_handler == NULL)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1647 return NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1648
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1649 memset(s, 0, sizeof(*s));
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1650 span_log_init(&s->logging, SPAN_LOG_NONE, NULL);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1651 span_log_set_protocol(&s->logging, "T.31");
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1652
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1653 s->modem_control_handler = modem_control_handler;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1654 s->modem_control_user_data = modem_control_user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1655 #if defined(ENABLE_V17)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1656 v17_rx_init(&(s->v17rx), 14400, non_ecm_put_bit, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1657 v17_tx_init(&(s->v17tx), 14400, FALSE, non_ecm_get_bit, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1658 #endif
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1659 v29_rx_init(&(s->v29rx), 9600, non_ecm_put_bit, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1660 v29_rx_signal_cutoff(&(s->v29rx), -45.5);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1661 v29_tx_init(&(s->v29tx), 9600, FALSE, non_ecm_get_bit, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1662 v27ter_rx_init(&(s->v27ter_rx), 4800, non_ecm_put_bit, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1663 v27ter_tx_init(&(s->v27ter_tx), 4800, FALSE, non_ecm_get_bit, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1664 silence_gen_init(&(s->silence_gen), 0);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1665 power_meter_init(&(s->rx_power), 4);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1666 s->last_sample = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1667 s->silence_threshold_power = power_meter_level_dbm0(-43);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1668 s->at_state.rx_signal_present = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1669 s->at_state.rx_trained = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1670
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1671 s->at_state.do_hangup = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1672 s->at_state.line_ptr = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1673 s->silence_heard = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1674 s->silence_awaited = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1675 s->call_samples = 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1676 s->modem = -1;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1677 s->at_state.transmit = TRUE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1678 s->rx_handler = dummy_rx;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1679 s->rx_user_data = NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1680 s->tx_handler = (span_tx_handler_t *) &silence_gen;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1681 s->tx_user_data = &(s->silence_gen);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1682
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1683 if (queue_create(&(s->rx_queue), 4096, QUEUE_WRITE_ATOMIC | QUEUE_READ_ATOMIC) < 0)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1684 return NULL;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1685 at_init(&s->at_state, at_tx_handler, at_tx_user_data, t31_modem_control_handler, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1686 at_set_class1_handler(&s->at_state, process_class1_cmd, s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1687 s->at_state.dte_inactivity_timeout = DEFAULT_DTE_TIMEOUT;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1688 if (tx_t38_packet_handler)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1689 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1690 t38_core_init(&s->t38, process_rx_indicator, process_rx_data, process_rx_missing, (void *) s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1691 s->t38.tx_packet_handler = tx_t38_packet_handler;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1692 s->t38.tx_packet_user_data = tx_t38_packet_user_data;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1693 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1694 s->t38_mode = FALSE;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1695 return s;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1696 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1697 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1698
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1699 int t31_release(t31_state_t *s)
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1700 {
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1701 at_reset_call_info(&s->at_state);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1702 free(s);
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1703 return 0;
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1704 }
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1705 /*- End of function --------------------------------------------------------*/
f762bf195c4b import spandsp-0.0.3
Peter Meerwald <pmeerw@cosy.sbg.ac.at>
parents:
diff changeset
1706 /*- End of file ------------------------------------------------------------*/

Repositories maintained by Peter Meerwald, pmeerw@pmeerw.net.