audiostuff: spandsp-0.0.6pre17/src/t30.c annotate

author	Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date	Fri, 25 Jun 2010 15:50:58 +0200
parents
children

rev	line source
4 26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	1 /*
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	2 * SpanDSP - a series of DSP components for telephony
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	3 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	4 * t30.c - ITU T.30 FAX transfer processing
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	5 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	6 * Written by Steve Underwood <steveu@coppice.org>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	7 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	8 * Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009 Steve Underwood
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	9 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	10 * All rights reserved.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	11 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	12 * This program is free software; you can redistribute it and/or modify
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	13 * it under the terms of the GNU Lesser General Public License version 2.1,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	14 * as published by the Free Software Foundation.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	15 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	16 * This program is distributed in the hope that it will be useful,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	19 * GNU Lesser General Public License for more details.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	20 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	21 * You should have received a copy of the GNU Lesser General Public
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	22 * License along with this program; if not, write to the Free Software
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	24 *
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	25 * $Id: t30.c,v 1.305.4.4 2009/12/23 14:23:49 steveu Exp $
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	26 */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	27
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	28 /! \file /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	29
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	30 #if defined(HAVE_CONFIG_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	31 #include "config.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	32 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	33
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	34 #include <stdlib.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	35 #include <stdio.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	36 #include <inttypes.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	37 #include <string.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	38 #include <fcntl.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	39 #include <time.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	40 #if defined(HAVE_TGMATH_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	41 #include <tgmath.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	42 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	43 #if defined(HAVE_MATH_H)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	44 #include <math.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	45 #endif
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	46 #include "floating_fudge.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	47 #include <tiffio.h>
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	48
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	49 #include "spandsp/telephony.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	50 #include "spandsp/logging.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	51 #include "spandsp/bit_operations.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	52 #include "spandsp/queue.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	53 #include "spandsp/power_meter.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	54 #include "spandsp/complex.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	55 #include "spandsp/tone_generate.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	56 #include "spandsp/async.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	57 #include "spandsp/hdlc.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	58 #include "spandsp/fsk.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	59 #include "spandsp/v29rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	60 #include "spandsp/v29tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	61 #include "spandsp/v27ter_rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	62 #include "spandsp/v27ter_tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	63 #include "spandsp/t4_rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	64 #include "spandsp/t4_tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	65 #include "spandsp/t30_fcf.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	66 #include "spandsp/t35.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	67 #include "spandsp/t30.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	68 #include "spandsp/t30_api.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	69 #include "spandsp/t30_logging.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	70
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	71 #include "spandsp/private/logging.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	72 #include "spandsp/private/t4_rx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	73 #include "spandsp/private/t4_tx.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	74 #include "spandsp/private/t30.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	75 #include "spandsp/private/t30_dis_dtc_dcs_bits.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	76
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	77 #include "t30_local.h"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	78
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	79 /! The maximum permitted number of retries of a single command allowed. /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	80 #define MAX_COMMAND_TRIES 3
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	81
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	82 /*! The maximum permitted number of retries of a single response request allowed. This
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	83 is not specified in T.30. However, if you don't apply some limit a messed up FAX
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	84 terminal could keep you retrying all day. Its a backstop protection. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	85 #define MAX_RESPONSE_TRIES 6
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	86
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	87 /* T.30 defines the following call phases:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	88 Phase A: Call set-up.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	89 Exchange of CNG, CED and the called terminal identification.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	90 Phase B: Pre-message procedure for identifying and selecting the required facilities.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	91 Capabilities negotiation, and training, up the the confirmation to receive.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	92 Phase C: Message transmission (includes phasing and synchronization where appropriate).
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	93 Transfer of the message at high speed.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	94 Phase D: Post-message procedure, including end-of-message and confirmation and multi-document procedures.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	95 End of message and acknowledgement.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	96 Phase E: Call release
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	97 Final call disconnect. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	98 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	99 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	100 T30_PHASE_IDLE = 0, /* Freshly initialised */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	101 T30_PHASE_A_CED, /* Doing the CED (answer) sequence */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	102 T30_PHASE_A_CNG, /* Doing the CNG (caller) sequence */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	103 T30_PHASE_B_RX, /* Receiving pre-message control messages */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	104 T30_PHASE_B_TX, /* Transmitting pre-message control messages */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	105 T30_PHASE_C_NON_ECM_RX, /* Receiving a document message in non-ECM mode */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	106 T30_PHASE_C_NON_ECM_TX, /* Transmitting a document message in non-ECM mode */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	107 T30_PHASE_C_ECM_RX, /* Receiving a document message in ECM (HDLC) mode */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	108 T30_PHASE_C_ECM_TX, /* Transmitting a document message in ECM (HDLC) mode */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	109 T30_PHASE_D_RX, /* Receiving post-message control messages */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	110 T30_PHASE_D_TX, /* Transmitting post-message control messages */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	111 T30_PHASE_E, /* In phase E */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	112 T30_PHASE_CALL_FINISHED /* Call completely finished */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	113 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	114
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	115 static const char *phase_names[] =
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	116 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	117 "T30_PHASE_IDLE",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	118 "T30_PHASE_A_CED",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	119 "T30_PHASE_A_CNG",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	120 "T30_PHASE_B_RX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	121 "T30_PHASE_B_TX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	122 "T30_PHASE_C_NON_ECM_RX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	123 "T30_PHASE_C_NON_ECM_TX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	124 "T30_PHASE_C_ECM_RX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	125 "T30_PHASE_C_ECM_TX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	126 "T30_PHASE_D_RX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	127 "T30_PHASE_D_TX",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	128 "T30_PHASE_E",
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	129 "T30_PHASE_CALL_FINISHED"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	130 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	131
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	132 /* These state names are modelled after places in the T.30 flow charts. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	133 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	134 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	135 T30_STATE_ANSWERING = 1,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	136 T30_STATE_B,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	137 T30_STATE_C,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	138 T30_STATE_D,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	139 T30_STATE_D_TCF,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	140 T30_STATE_D_POST_TCF,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	141 T30_STATE_F_TCF,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	142 T30_STATE_F_CFR,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	143 T30_STATE_F_FTT,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	144 T30_STATE_F_DOC_NON_ECM,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	145 T30_STATE_F_POST_DOC_NON_ECM,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	146 T30_STATE_F_DOC_ECM,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	147 T30_STATE_F_POST_DOC_ECM,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	148 T30_STATE_F_POST_RCP_MCF,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	149 T30_STATE_F_POST_RCP_PPR,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	150 T30_STATE_F_POST_RCP_RNR,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	151 T30_STATE_R,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	152 T30_STATE_T,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	153 T30_STATE_I,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	154 T30_STATE_II,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	155 T30_STATE_II_Q,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	156 T30_STATE_III_Q_MCF,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	157 T30_STATE_III_Q_RTP,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	158 T30_STATE_III_Q_RTN,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	159 T30_STATE_IV,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	160 T30_STATE_IV_PPS_NULL,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	161 T30_STATE_IV_PPS_Q,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	162 T30_STATE_IV_PPS_RNR,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	163 T30_STATE_IV_CTC,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	164 T30_STATE_IV_EOR,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	165 T30_STATE_IV_EOR_RNR,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	166 T30_STATE_CALL_FINISHED
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	167 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	168
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	169 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	170 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	171 T30_MIN_SCAN_20MS = 0,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	172 T30_MIN_SCAN_5MS = 1,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	173 T30_MIN_SCAN_10MS = 2,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	174 T30_MIN_SCAN_40MS = 4,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	175 T30_MIN_SCAN_0MS = 7,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	176 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	177
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	178 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	179 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	180 T30_MODE_SEND_DOC = 1,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	181 T30_MODE_RECEIVE_DOC
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	182 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	183
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	184 /*! These are internal assessments of received image quality, used to determine whether we
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	185 continue, retrain, or abandon the call. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	186 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	187 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	188 T30_COPY_QUALITY_PERFECT = 0,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	189 T30_COPY_QUALITY_GOOD,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	190 T30_COPY_QUALITY_POOR,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	191 T30_COPY_QUALITY_BAD
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	192 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	193
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	194 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	195 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	196 DISBIT1 = 0x01,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	197 DISBIT2 = 0x02,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	198 DISBIT3 = 0x04,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	199 DISBIT4 = 0x08,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	200 DISBIT5 = 0x10,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	201 DISBIT6 = 0x20,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	202 DISBIT7 = 0x40,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	203 DISBIT8 = 0x80
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	204 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	205
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	206 /*! There are high level indications of what is happening at any instant, to guide the cleanup
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	207 process if the call is abandoned. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	208 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	209 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	210 OPERATION_IN_PROGRESS_NONE = 0,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	211 OPERATION_IN_PROGRESS_T4_RX,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	212 OPERATION_IN_PROGRESS_T4_TX
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	213 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	214
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	215 /* All timers specified in milliseconds */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	216
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	217 /*! Time-out T0 defines the amount of time an automatic calling terminal waits for the called terminal
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	218 to answer the call.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	219 T0 begins after the dialling of the number is completed and is reset:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	220 a) when T0 times out; or
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	221 b) when timer T1 is started; or
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	222 c) if the terminal is capable of detecting any condition which indicates that the call will not be
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	223 successful, when such a condition is detected.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	224 The recommended value of T0 is 60+-5s. However, when it is anticipated that a long call set-up
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	225 time may be encountered, an alternative value of up to 120s may be used.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	226 NOTE - National regulations may require the use of other values for T0. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	227 #define DEFAULT_TIMER_T0 60000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	228
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	229 /*! Time-out T1 defines the amount of time two terminals will continue to attempt to identify each
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	230 other. T1 is 35+-5s, begins upon entering phase B, and is reset upon detecting a valid signal or
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	231 when T1 times out.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	232 For operating methods 3 and 4 (see 3.1), the calling terminal starts time-out T1 upon reception of
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	233 the V.21 modulation scheme.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	234 For operating method 4 bis a (see 3.1), the calling terminal starts time-out T1 upon starting
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	235 transmission using the V.21 modulation scheme.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	236 Annex A says T1 is also the timeout to be used for the receipt of the first HDLC frame after the
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	237 start of high speed flags in ECM mode. This seems a strange reuse of the T1 name, so we distinguish
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	238 it here by calling it T1A. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	239 #define DEFAULT_TIMER_T1 35000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	240 #define DEFAULT_TIMER_T1A 35000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	241
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	242 /*! Time-out T2 makes use of the tight control between commands and responses to detect the loss of
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	243 command/response synchronization. T2 is 6+-1s, and begins when initiating a command search
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	244 (e.g., the first entrance into the "command received" subroutine, reference flow diagram in section 5.2).
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	245 T2 is reset when an HDLC flag is received or when T2 times out. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	246 #define DEFAULT_TIMER_T2 7000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	247
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	248 /*! Once HDLC flags begin, T2 is reset, and a 3s timer begins. This timer is unnamed in T.30. Here we
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	249 term it T2A. No tolerance is specified for this timer. T2A specifies the maximum time to wait for the
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	250 end of a frame, after the initial flag has been seen. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	251 #define DEFAULT_TIMER_T2A 3000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	252
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	253 /*! If the HDLC carrier falls during reception, we need to apply a minimum time before continuing. If we
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	254 don't, there are circumstances where we could continue and reply before the incoming signals have
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	255 really finished. E.g. if a bad DCS is received in a DCS-TCF sequence, we need wait for the TCF
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	256 carrier to pass, before continuing. This timer is specified as 200ms, but no tolerance is specified.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	257 It is unnamed in T.30. Here we term it T2B */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	258 #define DEFAULT_TIMER_T2B 200
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	259
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	260 /*! Time-out T3 defines the amount of time a terminal will attempt to alert the local operator in
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	261 response to a procedural interrupt. Failing to achieve operator intervention, the terminal will
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	262 discontinue this attempt and shall issue other commands or responses. T3 is 10+-5s, begins on the
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	263 first detection of a procedural interrupt command/response signal (i.e., PIN/PIP or PRI-Q) and is
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	264 reset when T3 times out or when the operator initiates a line request. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	265 #define DEFAULT_TIMER_T3 15000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	266
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	267 /*! Time-out T4 defines the amount of time a terminal will wait for flags to begin, when waiting for a
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	268 response from a remote terminal. T2 is 3s +-15%, and begins when initiating a response search
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	269 (e.g., the first entrance into the "response received" subroutine, reference flow diagram in section 5.2).
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	270 T4 is reset when an HDLC flag is received or when T4 times out.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	271 NOTE - For manual FAX units, the value of timer T4 may be either 3.0s +-15% or 4.5s +-15%.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	272 If the value of 4.5s is used, then after detection of a valid response to the first DIS, it may
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	273 be reduced to 3.0s +-15%. T4 = 3.0s +-15% for automatic units. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	274 #define DEFAULT_TIMER_T4 3450
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	275
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	276 /*! Once HDLC flags begin, T4 is reset, and a 3s timer begins. This timer is unnamed in T.30. Here we
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	277 term it T4A. No tolerance is specified for this timer. T4A specifies the maximum time to wait for the
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	278 end of a frame, after the initial flag has been seen. Note that a different timer is used for the fast
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	279 HDLC in ECM mode, to provide time for physical paper handling. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	280 #define DEFAULT_TIMER_T4A 3000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	281
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	282 /*! If the HDLC carrier falls during reception, we need to apply a minimum time before continuing. if we
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	283 don't, there are circumstances where we could continue and reply before the incoming signals have
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	284 really finished. E.g. if a bad DCS is received in a DCS-TCF sequence, we need wait for the TCF
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	285 carrier to pass, before continuing. This timer is specified as 200ms, but no tolerance is specified.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	286 It is unnamed in T.30. Here we term it T4B */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	287 #define DEFAULT_TIMER_T4B 200
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	288
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	289 /*! Time-out T5 is defined for the optional T.4 error correction mode. Time-out T5 defines the amount
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	290 of time waiting for clearance of the busy condition of the receiving terminal. T5 is 60+-5s and
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	291 begins on the first detection of the RNR response. T5 is reset when T5 times out or the MCF or PIP
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	292 response is received or when the ERR or PIN response is received in the flow control process after
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	293 transmitting the EOR command. If the timer T5 has expired, the DCN command is transmitted for
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	294 call release. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	295 #define DEFAULT_TIMER_T5 65000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	296
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	297 /*! (Annex C - ISDN) Time-out T6 defines the amount of time two terminals will continue to attempt to
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	298 identify each other. T6 is 5+-0.5s. The timeout begins upon entering Phase B, and is reset upon
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	299 detecting a valid signal, or when T6 times out. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	300 #define DEFAULT_TIMER_T6 5000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	301
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	302 /*! (Annex C - ISDN) Time-out T7 is used to detect loss of command/response synchronization. T7 is 6+-1s.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	303 The timeout begins when initiating a command search (e.g., the first entrance into the "command received"
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	304 subroutine - see flow diagram in C.5) and is reset upon detecting a valid signal or when T7 times out. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	305 #define DEFAULT_TIMER_T7 7000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	306
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	307 /*! (Annex C - ISDN) Time-out T8 defines the amount of time waiting for clearance of the busy condition
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	308 of the receiving terminal. T8 is 10+-1s. The timeout begins on the first detection of the combination
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	309 of no outstanding corrections and the RNR response. T8 is reset when T8 times out or MCF response is
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	310 received. If the timer T8 expires, a DCN command is transmitted for call release. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	311 #define DEFAULT_TIMER_T8 10000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	312
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	313 /*! Final time we allow for things to flush through the system, before we disconnect, in milliseconds.
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	314 200ms should be fine for a PSTN call. For a T.38 call something longer is desirable. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	315 #define FINAL_FLUSH_TIME 1000
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	316
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	317 /*! The number of PPRs received before CTC or EOR is sent in ECM mode. T.30 defines this as 4,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	318 but it could be varied, and the Japanese spec, for example, does make this value a
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	319 variable. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	320 #define PPR_LIMIT_BEFORE_CTC_OR_EOR 4
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	321
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	322 /* HDLC message header byte values */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	323 #define ADDRESS_FIELD 0xFF
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	324 #define CONTROL_FIELD_NON_FINAL_FRAME 0x03
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	325 #define CONTROL_FIELD_FINAL_FRAME 0x13
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	326
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	327 enum
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	328 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	329 TIMER_IS_IDLE = 0,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	330 TIMER_IS_T2,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	331 TIMER_IS_T1A,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	332 TIMER_IS_T2A,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	333 TIMER_IS_T2B,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	334 TIMER_IS_T2C,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	335 TIMER_IS_T4,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	336 TIMER_IS_T4A,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	337 TIMER_IS_T4B,
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	338 TIMER_IS_T4C
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	339 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	340
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	341 /* Start points in the fallback table for different capabilities */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	342 /! The starting point in the modem fallback sequence if V.17 is allowed /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	343 #define T30_V17_FALLBACK_START 0
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	344 /! The starting point in the modem fallback sequence if V.17 is not allowed /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	345 #define T30_V29_FALLBACK_START 3
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	346 /! The starting point in the modem fallback sequence if V.29 is not allowed /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	347 #define T30_V27TER_FALLBACK_START 6
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	348
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	349 static const struct
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	350 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	351 int bit_rate;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	352 int modem_type;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	353 int which;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	354 uint8_t dcs_code;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	355 } fallback_sequence[] =
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	356 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	357 {14400, T30_MODEM_V17, T30_SUPPORT_V17, DISBIT6},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	358 {12000, T30_MODEM_V17, T30_SUPPORT_V17, (DISBIT6 \| DISBIT4)},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	359 { 9600, T30_MODEM_V17, T30_SUPPORT_V17, (DISBIT6 \| DISBIT3)},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	360 { 9600, T30_MODEM_V29, T30_SUPPORT_V29, DISBIT3},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	361 { 7200, T30_MODEM_V17, T30_SUPPORT_V17, (DISBIT6 \| DISBIT4 \| DISBIT3)},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	362 { 7200, T30_MODEM_V29, T30_SUPPORT_V29, (DISBIT4 \| DISBIT3)},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	363 { 4800, T30_MODEM_V27TER, T30_SUPPORT_V27TER, DISBIT4},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	364 { 2400, T30_MODEM_V27TER, T30_SUPPORT_V27TER, 0},
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	365 { 0, 0, 0, 0}
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	366 };
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	367
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	368 static void queue_phase(t30_state_t *s, int phase);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	369 static void set_phase(t30_state_t *s, int phase);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	370 static void set_state(t30_state_t *s, int state);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	371 static void send_simple_frame(t30_state_t *s, int type);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	372 static void send_frame(t30_state_t s, const uint8_t fr, int frlen);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	373 static void send_dcn(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	374 static void repeat_last_command(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	375 static void disconnect(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	376 static void decode_20digit_msg(t30_state_t s, char msg, const uint8_t *pkt, int len);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	377 static void decode_url_msg(t30_state_t s, char msg, const uint8_t *pkt, int len);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	378 static int set_min_scan_time_code(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	379 static int send_cfr_sequence(t30_state_t *s, int start);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	380 static void timer_t2_start(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	381 static void timer_t2a_start(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	382 static void timer_t2b_start(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	383 static void timer_t4_start(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	384 static void timer_t4a_start(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	385 static void timer_t4b_start(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	386 static void timer_t2_t4_stop(t30_state_t *s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	387
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	388 /! Test a specified bit within a DIS, DTC or DCS frame /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	389 #define test_ctrl_bit(s,bit) ((s)[3 + ((bit - 1)/8)] & (1 << ((bit - 1)%8)))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	390 /! Set a specified bit within a DIS, DTC or DCS frame /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	391 #define set_ctrl_bit(s,bit) (s)[3 + ((bit - 1)/8)] \|= (1 << ((bit - 1)%8))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	392 /! Set a specified block of bits within a DIS, DTC or DCS frame /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	393 #define set_ctrl_bits(s,val,bit) (s)[3 + ((bit - 1)/8)] \|= ((val) << ((bit - 1)%8))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	394 /! Clear a specified bit within a DIS, DTC or DCS frame /
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	395 #define clr_ctrl_bit(s,bit) (s)[3 + ((bit - 1)/8)] &= ~(1 << ((bit - 1)%8))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	396
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	397 static int terminate_operation_in_progress(t30_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	398 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	399 /* Make sure any FAX in progress is tidied up. If the tidying up has
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	400 already happened, repeating it here is harmless. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	401 switch (s->operation_in_progress)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	402 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	403 case OPERATION_IN_PROGRESS_T4_TX:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	404 t4_tx_release(&s->t4);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	405 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	406 case OPERATION_IN_PROGRESS_T4_RX:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	407 t4_rx_release(&s->t4);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	408 break;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	409 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	410 s->operation_in_progress = OPERATION_IN_PROGRESS_NONE;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	411 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	412 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	413 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	414
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	415 static int tx_start_page(t30_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	416 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	417 if (t4_tx_start_page(&s->t4))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	418 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	419 terminate_operation_in_progress(s);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	420 return -1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	421 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	422 s->ecm_block = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	423 s->error_correcting_mode_retries = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	424 span_log(&s->logging, SPAN_LOG_FLOW, "Starting page %d of transfer\n", s->tx_page_number + 1);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	425 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	426 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	427 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	428
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	429 static int tx_end_page(t30_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	430 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	431 s->retries = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	432 if (t4_tx_end_page(&s->t4) == 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	433 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	434 s->tx_page_number++;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	435 s->ecm_block = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	436 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	437 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	438 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	439 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	440
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	441 static int rx_start_page(t30_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	442 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	443 int i;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	444
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	445 t4_rx_set_image_width(&s->t4, s->image_width);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	446 t4_rx_set_sub_address(&s->t4, s->rx_info.sub_address);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	447 t4_rx_set_dcs(&s->t4, s->rx_dcs_string);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	448 t4_rx_set_far_ident(&s->t4, s->rx_info.ident);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	449 t4_rx_set_vendor(&s->t4, s->vendor);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	450 t4_rx_set_model(&s->t4, s->model);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	451
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	452 t4_rx_set_rx_encoding(&s->t4, s->line_encoding);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	453 t4_rx_set_x_resolution(&s->t4, s->x_resolution);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	454 t4_rx_set_y_resolution(&s->t4, s->y_resolution);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	455
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	456 if (t4_rx_start_page(&s->t4))
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	457 return -1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	458 /* Clear the buffer */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	459 for (i = 0; i < 256; i++)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	460 s->ecm_len[i] = -1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	461 s->ecm_block = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	462 s->ecm_frames = -1;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	463 s->ecm_frames_this_tx_burst = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	464 s->error_correcting_mode_retries = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	465 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	466 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	467 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	468
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	469 static int rx_end_page(t30_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	470 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	471 if (t4_rx_end_page(&s->t4) == 0)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	472 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	473 s->rx_page_number++;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	474 s->ecm_block = 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	475 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	476 return 0;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	477 }
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	478 /- End of function --------------------------------------------------------/
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	479
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	480 static int copy_quality(t30_state_t *s)
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	481 {
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	482 t4_stats_t stats;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	483 int quality;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	484
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	485 t4_get_transfer_statistics(&s->t4, &stats);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	486 /* There is no specification for judging copy quality. However, we need to classify
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	487 it at three levels, to control what we do next: OK; tolerable, but retrain;
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	488 intolerable. */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	489 /* Based on the thresholds used in the TSB85 tests, we consider:
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	490 <5% bad rows is OK
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	491 <15% bad rows to be tolerable, but retrain
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	492 >15% bad rows to be intolerable
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	493 */
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	494 span_log(&s->logging, SPAN_LOG_FLOW, "Page no = %d\n", stats.pages_transferred + 1);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	495 span_log(&s->logging, SPAN_LOG_FLOW, "Image size = %d x %d pixels\n", stats.width, stats.length);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	496 span_log(&s->logging, SPAN_LOG_FLOW, "Image resolution = %d/m x %d/m\n", stats.x_resolution, stats.y_resolution);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	497 span_log(&s->logging, SPAN_LOG_FLOW, "Bad rows = %d\n", stats.bad_rows);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	498 span_log(&s->logging, SPAN_LOG_FLOW, "Longest bad row run = %d\n", stats.longest_bad_row_run);
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	499 /* Don't treat a page as perfect because it has zero bad rows out of zero total rows. A zero row
26cd8f1ef0b1 import spandsp-0.0.6pre17 Peter Meerwald <pmeerw@cosy.sbg.ac.at> parents: diff changeset	500 page has got to be some kind of total page failure. */

4

26cd8f1ef0b1 import spandsp-0.0.6pre17